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MAR 24, 2020InterMotion Technology boosts IP verification productivity for Lattice Semiconductor’s CrossLink FPGA family using Aldec’s Active-HDL
MAR 02, 2020Aldec to Present at Certification Together International Conference
FEB 19, 2020Aldec and Codasip at Embedded World: Showcasing an Integrated UVM Simulation Environment for Verifying Custom Instructions with RISC-V Cores
JAN 28, 2020Cobham Gaisler successfully verifies its first RISC-V processor, NOEL-V, using Aldec’s Riviera-PRO for HDL Simulation
DEC 17, 2019Aldec Enhances Riviera-PRO’s VHDL and UVVM Support
DEC 12, 2019Aldec’s new FPGA-based NVMe Data Storage Solution Targets High Performance Computing Applications
DEC 03, 2019Aldec’s Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM
NOV 26, 2019Aldec’s Latest Embedded Development Platform is First to Feature Largest PolarFire and SmartFusion2 FPGAs on a Single Board
NOV 26, 2019Developing Robust Finite State Machines Code With Lint Tools
NOV 18, 2019Aldec at SC19: Showcasing Multi-FPGA Partitioning Software for Multi-FPGA-based Algorithm Accelerators
NOV 14, 2019Aldec Provides the Industry’s Most-Comprehensive Portfolio of FMC Daughter Cards
OCT 21, 2019Aldec at DVCon Europe: Demonstrating a hybrid co-verification platform for ASIC/SoC projects and automated FPGA partitioning software
OCT 02, 2019Aldec’s Focus for Arm TechCon is on Deep Neural Network and Machine Learning Application Development
SEP 24, 2019Aldec cuts ASIC design prototype bring-up time with HES-DVM’s automatic partitioning tool and faster HDL-to-FPGA compilation times
SEP 09, 2019SoC & ASIC designers to benefit greatly from multiple HES Proto-AXI™ enhancements
JUN 18, 2019Riviera-PRO™ users to benefit from automatic UVM register generation plus the latest verification methodology libraries
JUN 03, 2019Introducing SyntHESer, Aldec’s proprietary high-speed synthesizer for HES emulation and prototyping
MAY 15, 2019Aldec @ DAC 2019: Celebrating its 35th Anniversary and focusing on design acceleration, co-verification and mixed-signal
APR 01, 2019Hardware Lifecycle Data Management for Teams
FEB 26, 2019Latest TySOM Kit Accelerates the Development of AI, DNN and Other Algorithm Acceleration-dependent Applications Plus Aids SoC Prototyping
JAN 22, 2019Aldec facilitates design prototyping in FPGA and prototype testing with new HES Proto-AXI
JAN 14, 2019Aldec shortens time of ASIC design prototype bring-up in FPGA with HES-DVM Proto mode
NOV 13, 2018VHDL 2018 Support & Enhanced Automation - Aldec adds VHDL Standard 1076-2018 extensions and automatic coverage model generation to Riviera-PRO™
OCT 22, 2018Aldec’s “Hardware and Software Co-verification in Hybrid Simulation and Emulation Environment with QEMU” DVCon Europe tutorial to demonstrate how engineers can obtain a holistic view over their SoC design
OCT 15, 2018A View from Above
OCT 15, 2018Visible Benefits
AUG 08, 2018SemiWiki: Enhancing Early Static FSM
JUL 20, 2018Aldec to Present at the 6th China National FPGA Industry Development Forum
JUL 19, 2018Enhanced early static checks of Finite State Machines and Xilinx IP-based designs
JUN 11, 2018SemiWiki: RAL, Lint and VHDL-2018
JUN 07, 2018Aldec @ DAC 2018: Presenting Innovative SoC Design & Verification Methodologies
MAY 08, 2018Three Enhancements in One - Aldec bolsters Riviera-PRO™ with automatic UVM register generation, Unit Linting and the ability to handle early VHDL 2018 extensions
MAY 02, 2018Aldec and Tamba Networks Release Ultra Low Latency Ethernet Solution for UltraScale+ FPGA at The Trading Show 2018
APR 18, 2018SemiWiki: RDC - A Cousin To CDC
APR 11, 2018Aldec’s HES UltraScale+ Reconfigurable Accelerator and Northwest Logic’s PCI Express Cores Provide Proven PCI Express Solution
MAR 12, 2018SemiWiki: Clock Domain Crossing in FPGA
FEB 21, 2018Aldec to showcase Verification Spectrum for SoC FPGAs at Embedded World 2018
FEB 20, 2018QuickLogic Announces Partnership with Aldec for eFPGA Simulation Flow
FEB 08, 2018Aldec presents ‘Dealing with CDC verification complexity in large-scale FPGA designs’ at FPGA Forum 2018
FEB 07, 2018Reconfigurable high-performance routers and switches - made easy
FEB 05, 2018Engineering Productivity Improved through Early Code Quality Checks
JAN 30, 2018SemiWiki: Conflating ISO 26262 and DO-254
JAN 17, 2018Assure robustness of Finite State Machines and Reset Domain Crossings – via early static checks
DEC 21, 2017Aldec and High-Performance Computing
DEC 13, 2017Aldec releases re-configurable FPGA-based accelerators for High Frequency Trading applications
NOV 15, 2017Hardware and software engineers designing SoC FPGAs stand to profit from Aldec QEMU Bridge
NOV 15, 2017Living on the Edge
NOV 09, 2017Aldec to showcase FPGA-based algorithm accelerators at SC17
OCT 23, 2017Aldec unveils Zynq™ MPSoC ZU7EV Embedded Board at ARM TechCon 2017
OCT 10, 2017SemiWiki: An IIot Gateway to the Cloud
OCT 09, 2017Aldec to Present Software Driven Test of FPGA Prototype @ DVCon Europe 2017
SEP 19, 2017SemiWiki: Partitioning for Prototypes
SEP 17, 2017Aldec presents 'HDL Coding Standards and Best Practices for DO-254’ tutorial at the 36th Annual DASC
SEP 12, 2017Aldec @ DVCon India 2017 - accelerating SoC validation by extending QEMU open-source capabilities
SEP 11, 2017Aldec solves ASIC design partitioning challenges with HES-DVM Proto mode
SEP 01, 2017Intelligent Aerospace: Reprogrammable prototyping solutions: a must for space design verification
AUG 30, 2017Embedded Vision: Look and Identify
AUG 08, 2017Benefit from the power of the latest SystemVerilog subset constructs – with confidence
AUG 02, 2017SemiWiki: Cloud-Based Emulation
JUL 03, 2017SemiWiki: HW and SW Co-verification for Xilinx Zynq SoC FPGAs
JUN 15, 2017Aldec and Silvaco present Mixed-Signal Simulation Solution at DAC 2017
JUN 06, 2017Aldec @ DAC 2017: Presenting Breakthrough Innovations in SoC Design & Verification
JUN 06, 2017EE Web: The Benefits of HW/SW Co-Simulation for Zynq-Based Designs
MAY 30, 2017Intelligent Areospace: In safe hands: requirement-based testing for design assurance of complex, safety-critical components with high impacts of failure
MAY 29, 2017SemiWiki Interviews Dr. Stanley Hyduke, founder and CEO of Aldec
MAY 16, 2017Aldec to Showcase new Xilinx UltraScale FPGA Accelerator board for High Frequency Trading Applications at The Trading Show 2017 in Chicago
MAY 16, 2017SemiWiki: High Frequency Trading and EDA
MAY 01, 2017Aldec unveils the newest Xilinx Zynq-based TySOM Embedded Prototyping Board at Embedded Vision Summit 2017
APR 26, 2017A Self-Contained Software-Driven Prototype
APR 24, 2017RTL Linting: Proceed with Confidence
APR 18, 2017Q&A with Louie De Luna, Director of Marketing at ALDEC
APR 17, 2017Aldec to Demonstrate Design Verification Techniques with Hardware-In-The-Loop and QEMU at DvCON China 2017
APR 11, 2017Aldec continues to stack up pre-compiled verification libraries and delivers significant SystemVerilog and UVM speedup with latest release of Riviera-PRO
APR 07, 2017Safety Assured
MAR 17, 2017SemiWiki: Aldec Swings for the Fences
MAR 15, 2017Aldec Celebrates 10 Years in DO-254 at Certification Together International Conference
MAR 07, 2017Aldec Introduces End-to-end HW/SW Co-verification for Xilinx Zynq SoC FPGAs at Embedded World 2017
FEB 28, 2017Aldec unveils Xilinx UltraScale FPGA-based prototyping board enabling Simulation Acceleration and Emulation with the latest release of HES-DVM
FEB 23, 2017Aldec to Demonstrate UVM Simulation Acceleration with Network-On-Chip (NoC) Demo Design at DVCon U.S. 2017
FEB 23, 2017Better Code With RTL Linting And CDC Verification
FEB 21, 2017Aldec to Showcase FPGA Acceleration of Genome Alignment, Motion Detection and Face Detection Algorithms at isFPGA 2017
FEB 16, 2017Aldec Rounds Out ALINT-PRO Checker
FEB 14, 2017Aldec sets a new paradigm with a single platform for Design Rule Checking and Clock Domain Crossing Verification for FPGA and ASIC designs
FEB 01, 2017Aldec delivers DO-254 Compliant Templates and Checklists with the latest release of Spec-TRACER
JAN 19, 2017Aldec provides Finite State Machine Coverage for verification of safety-critical FPGAs
DEC 07, 2016Top Aldec Design and Verification Blog Articles from 2016
NOV 16, 2016Aldec delivers significant SystemVerilog speedup and a pioneering initiative for VHDL users with latest Riviera-PRO
NOV 14, 2016Aldec and Indian Institute of Science faculty enterprise, ReneLife, showcase ReneGENE for accurate genome alignment on HES Accelerator at SC16
NOV 14, 2016SemiWiki: 3 in 1 Hardware Verification
NOV 10, 2016Aldec adds largest Xilinx UltraScale to latest HES Solution for FPGA Simulation Acceleration, Emulation, and Prototyping to be unveiled at SemIsrael 2016
OCT 27, 2016Semiconductor Engineering: Emulation’s Footprint Grows
OCT 27, 2016Semiconductor Engineering: Too Big To Simulate?
OCT 24, 2016SemiWiki: FPGAs for a few thousand devices more
OCT 20, 2016Aldec to Showcase Xilinx Zynq-based ADAS and IoT Gateway Development Platforms at ARM TechCon 2016
OCT 11, 2016Aldec to Highlight ASIC Pre-Silicon Verification Spectrum with Network-On-Chip (NoC) Demonstration at DVCon Europe
SEP 19, 2016SemiWiki: Up front phases improve CDC analysis
SEP 05, 2016Intelligent Aerospace: FPGA verification techniques for avionics applications
AUG 17, 2016SemiWiki: Optimization and verification wins in IoT designs
AUG 16, 2016Aldec Delivers Verification Support for Embedded Applications with New Xilinx Zynq-based TySOM Embedded Development Kit
AUG 15, 2016Embedded Computing Design: Verification is crucial for programmable SoC designs
JUL 12, 2016Aldec Increases Verification Productivity with the latest release of Riviera-PRO
MAY 24, 2016Aldec @ DAC 2016: Scalable Emulation, Prototyping, IoT, ASIC Verification Spectrum and More
MAY 17, 2016Aldec Extends Spectrum of Verification Tools for Use in Digital ASIC Designs
MAR 16, 2016Aldec to Offer Complete Coverage Analysis with the Addition of Condition and Path Coverage to Active-HDL’s Powerful Coverage Database
MAR 15, 2016Aldec Introduces SCE-MI Pipes-based Flow for Streaming High-volume Data and 30% Speed Increase with Latest Release of HES-DVM
MAR 11, 2016Design units come to faster Riviera-PRO release
MAR 09, 2016Aldec delivers enhanced UVM Support and New Debugging Features with the latest release of Riviera-PRO
FEB 26, 2016Aldec reprograms HES7 for AXI4 speed
FEB 24, 2016Aldec to unveil HES-7 High-speed AXI Transmission Channel at DVCon 2016
FEB 03, 2016Updated tool cuts through DO-254 V&V chaos
FEB 02, 2016Aldec Streamlines Management of DO-254 Validation and Verification with Spec-TRACER™
FEB 02, 2016FirstEDA to introduce Aldec’s FPGA Co-emulator at Verification Futures Europe
DEC 21, 2015Helpful Aldec Design and Verification Blog Articles from 2015
DEC 15, 2015Push the UVM start button then hit the accelerator, Part 2
NOV 10, 2015Push the UVM Start Button then Hit the Accelerator
NOV 04, 2015DVCon Europe “must see”: Aldec tutorial and demonstration on adopting Easier UVM to enable FPGA-based Acceleration
OCT 29, 2015Say Hi To Hybrid: ARM Fast Models meet Aldec Emulation
OCT 29, 2015Aldec HES™ Co-emulation named a finalist in this year’s ARM® TechCon Innovation Challenge
OCT 27, 2015Aldec Introduces Hybrid Emulation with ARM® Fast Model Support
OCT 20, 201550+ Successful DO-254 Projects Supported by Aldec’s FPGA Test System; Now with Pre-Tool Qualification Data Package
AUG 31, 2015EE Times: Hybrid Emulation: It's about time!
AUG 10, 2015Aldec enhances ALINT-PRO-CDC with Advanced Violation Analysis Capabilities and an Extended Set of Dynamic Checks
JUL 30, 2015Aldec delivers complete Coverage Analysis for FPGA and ASIC Designers with the latest release of Riviera-PRO
JUL 06, 2015Aldec to offer DAC Technical Sessions Live Online
JUL 02, 2015Semiconductor Engineering: UVM: What’s Stopping You?
JUN 01, 2015Concept Engineering′s Nlview™ Schematic Visualization Engine to Power Aldec′s ALINT-PRO-CDC™ CDC Verification Solution
JUN 01, 2015SemiWiki: Aldec packs 6 UltraScale parts on HES-7
MAY 28, 2015Scale & Scalability -- The Keys to True FPGA-Based Verification
MAY 27, 2015Aldec HES-7 with Xilinx Virtex UltraScale Devices Enables True FPGA-based Verification
MAY 26, 2015Aldec @ DAC 2015: Scalable Prototyping, UVM Simulation, Productivity Gains using Python and More
MAY 13, 2015Chip Design: CDC Verification: Using Both Static and Dynamic Checking is Key to Success
MAY 13, 2015Embedded Computing Design: You needn't decide between prototype or emulation
MAY 04, 2015Xilinx Accelerates System Verification with Vivado Design Suite 2015.1
MAR 10, 2015Aldec Delivers Support for Test Ranking in Code Coverage Analysis
FEB 18, 2015Aldec to deliver DO-254 Hardware Testing Presentation at Certification Together Intl. Conference (CTIC)
FEB 09, 2015Aldec Announces HES-7, the Largest Off-The-Shelf Xilinx Virtex-7 FPGA Prototyping System at up to 288 Million ASIC Gates Capacity
JAN 29, 2015Aldec launches ALINT-PRO-CDC™ delivering comprehensive CDC Verification Strategies for SoC and FPGA Designs
JAN 19, 2015Aldec Increasing the Return on Simulation
JAN 15, 2015Aldec Delivers Unprecedented Scalability and Verification Acceleration with the Latest Release of HES-DVM™
DEC 23, 2014Embedded Computing Design: Top five reasons why you need Requirements Traceability
DEC 10, 2014Aldec extends DOORS® Traceability to FPGA/SoC designs with Spec-TRACER™
DEC 08, 2014Aldec Releases Active-HDL 10.1 with 64-bit simulation support
NOV 29, 2014Verification Plans Overcome Hope-Based Coverage
NOV 12, 2014Aldec Delivers Efficient Verification with Requirements-based, User-defined Test Plan in Coverage
OCT 25, 20143 Reasons to Focus on Hardware Dependent Software
OCT 07, 2014Putting the ‘A’ in EDA
OCT 02, 2014Aldec and FTD Solutions Ink Distribution Agreement for Southeast Asia
SEP 29, 2014Aldec Serves up Emulation and Static Design Rule Check Solutions at 10th annual ARM TechCon Conference
SEP 26, 2014Dominating FPGA Clock Domains and CDCs
SEP 23, 2014Aldec Distributor, Prodigy Technovations, to Showcase Aldec Advanced Verification Platforms at DVCon India
SEP 08, 2014Aldec to Demonstrate Support for Xilinx UltraSCALE and SoC at X-Fest Events in North America
AUG 14, 2014Announcement: Riviera-PRO EDU Available on EDA Playground
AUG 05, 2014Aldec delivers Rapid Debugging with UVM Toolbox™ to Interpret Complex UVM Verification Environments
JUL 31, 2014Semiwiki: Then, Python walked in for verification
JUN 26, 2014Semiwiki: Real FPGAs don’t eat fake test vectors
JUN 23, 2014Aldec to offer ‘DAC CHAT’ Technical Sessions Live Online
JUN 17, 2014Semiwiki: Aldec Can Ensure Smooth System Integration
JUN 16, 2014Elbit Systems deploys Aldec DO-254/CTS and Passes EASA Verification Audit for Level A System
MAY 30, 2014Why Aldec’s Long-Term VP, Dave Rinehart, Is No Longer with The Company?
MAY 02, 2014Semiwiki: Aldec is Celebrating 30 Years @ #51DAC!
APR 30, 2014Aldec Celebrates 30 Years in EDA: Presenting Advanced Verification and Emulation Solutions at DAC 2014
APR 22, 2014Semiwiki: Learning an HDL Simulator
APR 22, 2014Semiwiki: You didn’t say it has to work
MAR 19, 2014Semiwiki: Aldec the leader in DO254
MAR 11, 2014Semiwiki: Now even I can spot bad UVM
MAR 05, 2014Aldec Presents a Visual Mapping Solution to Capture a Bird’s-eye View of UVM Verification Environments
FEB 28, 2014Semiwiki: Locked on FPGA design brand recognition
JAN 28, 2014Aldec solves another DO-254 challenge with Requirements Reviewer in Spec-TRACER™
JAN 16, 2014Top Aldec.com White Paper Downloads from 2013
JAN 06, 2014Top 10 Aldec Design and Verification Blog Articles from 2013
DEC 19, 2013Celebrate The Season All Over the World with Aldec
DEC 10, 2013Oki Information Systems® Leverages Aldec® Advanced Verification Solutions for Xilinx® FPGA Design
NOV 25, 2013NEC Corporation Adopts Aldec® ALINT™ for Communication Systems LSI Design
NOV 12, 2013Aldec Offers a Visual Approach to Debugging X-Issues in Simulation
NOV 04, 2013SemiWiki: I could show you the FPGA, but then I’d have to configure you
OCT 23, 2013Aldec delivers Global Project Management for Complex FPGA Designs with the latest release of Active-HDL™
SEP 23, 2013Aldec HES-7 SoC Prototyping Solution Adopted by Kumamoto University in Japan
AUG 26, 2013Aldec’s Active-HDL Celebrates Sweet 16 with Another Top FPGA Design Award
JUL 31, 2013Aldec and NEC Corp. Ink Distributorship Agreement for CyberWorkBench® ASIC/FPGA High Level Synthesis Solution
JUL 11, 2013Aldec Verifies Compatibility of Northwest Logic’s PCI Express Cores with HES-7™ SoC/ASIC Prototyping Platform
JUL 10, 2013Aldec Enables Class Hierarchy Visualization for UVM-Based Verification Environments
JUN 11, 2013Missed DAC? Aldec to offer Technical Sessions Online
MAY 20, 2013Aldec launches Spec-TRACER™ – Requirements Lifecycle Management for Safety-critical FPGA and ASIC Designs
MAY 15, 2013Aldec @ DAC 2013: Advanced Verification, HW/SW Emulation, SoC/ASIC Prototyping and more
APR 29, 2013Aldec Israel to Showcase Innovative Functional Verification Solutions at ChipEx2013 in Tel Aviv
APR 08, 2013Aldec Presents at Military & Aerospace Programmable Logic Devices Symposium (MAPLD)
APR 04, 2013DSP Survey, Solutions and Resources
MAR 28, 2013The latest in SoC and ASIC Prototyping News, Events and Resources
MAR 21, 2013New Electronics: ASIC/SoC Prototyping Platforms Increase Productivity
MAR 21, 2013Semiwiki: Plotting to take over the time-domain only world
MAR 11, 2013Aldec Releases Plot Window to Increase Productivity of Traditional Waveform-Based HDL Debugging
MAR 08, 2013EDA Café interviews Aldec Director of Sales, Keith McCann, at DVCon 2013
FEB 27, 2013The latest in ASIC Prototyping News, Events and Resources
FEB 26, 2013Aldec offers Advanced Screening of Functional Verification Platform’s Latest Release at DVCon 2013
FEB 25, 2013Aldec Adds Assertions Training to Fast Track Online Program
FEB 04, 2013Aldec Launches Free Online UVM Training
JAN 29, 2013Follow Aldec. Win a Kindle Fire HD.
JAN 07, 2013Hitachi Cable, Ltd. Deploys ALINT™ on Next Generation FPGA Design
JAN 02, 2013Aldec Emulation and Verification Tools Adopted by Taiwan National Chiao Tung University for ESL Design Master’s Program
DEC 20, 2012Aldec Optimizes FPGA Routing Resources for Power and Performance
DEC 17, 2012Now Available - Verification White Papers
DEC 12, 2012EE TIMES: Mil-Aero Top 10 'How-To' articles for 2012, FPGA testing for DO-254 Compliance by Aldec
DEC 12, 2012SEMIWIKI: Zynq out of the box, in FPGA-based Prototyping
DEC 10, 2012Aldec Adds ARM Cortex-A9 Support to HES-7 ASIC Prototyping Platform
DEC 04, 2012"Best of 2012" Top Webinars
DEC 03, 2012Aldec unwraps SoC/ASIC verification platform at ‘Verification Futures 2012’ in Europe
NOV 14, 2012Creonic Joins Aldec UNITE™ Partner Programme and Accelerates the Development of its IP Cores with Aldec Linting and Advanced Verification Tools
NOV 05, 2012Aldec Boosts VHDL Simulation Performance
NOV 05, 2012Aldec gives SoC Software Engineers early access to Hardware Aldec Inc. presents on Platform Validation at Verification Futures 2012
OCT 29, 2012EE Journal Chalk Talk “Integrated Design Environment for FPGA” With Aldec Product Manager, Satyam Jani
SEP 24, 2012Aldec Enhances Award-Winning Active-HDL with Flexible File Management to Manage Complex FPGA Projects
SEP 17, 2012Aldec Enters ASIC Prototyping Market with HES-7™ Leveraging Xilinx’s Virtex®-7, HES-7 expands up to 96m ASIC Gate Capacity
AUG 15, 2012SOC Central: Verific Design Automation's SystemVerilog, VHDL Parsers Linked with Aldec's Hardware Emulation Solution
JUL 18, 2012Q3-2012 - Aldec™ Design and Verification Newsletter
JUL 17, 2012TVS Validates UVM based VIP with Aldec’s Riviera-PRO Platform
JUL 10, 2012Aldec and Agilent Technologies Bridge the Gap Between ESL and RTL by Linking Simulation Environments
JUL 03, 2012Aldec invited to present "FPGA Level In-Target Testing for DO-254 Compliance" at Avionics Conference in South Korea
JUN 13, 2012EDACafe: Aldec Update with Al the Robot and App. Engineering Director, Igor Tsapenko
JUN 12, 2012DAC 2012 Wrap Up
JUN 06, 2012EE Times: FPGA-based SoC Verification Challenges
JUN 06, 2012Tech Design Forum: Where there’s a will… there’s a way to better VHDL verification
MAY 31, 2012Open-Source VHDL Verification Methodology (OS-VVM) User Group to unveil Advanced Test Methodologies for VHDL Designers at DAC
MAY 23, 2012Aldec at DAC 2012: 10 Face-to-Face Sessions
MAY 22, 2012EE Times: FPGA Testing for DO-254 Compliance
MAY 22, 2012Sigasi integrates Aldec Simulator to Accelerate Feedback Cycle
MAY 21, 2012Tanner EDA and Aldec Deliver High-performance A/MS Solution for Mixed-signal IC Design and Verification
MAY 09, 2012Verified: the need for continued VHDL support
MAY 08, 2012EE Journal: Aldec Harnesses Massive Server Capacity
MAY 01, 2012Aldec Israel to Serve Up the Latest in Functional Verification at ChipEx2012 in Tel Aviv
APR 18, 2012Aldec Solutions Support Hardware Architecture of Zynq EPP at X-Fest 2012
APR 12, 2012Q2-2012 - Aldec™ Design and Verification Newsletter
APR 11, 2012EE Times: Automatic C-to-VHDL Testbench Generation Shortens FPGA Development Time
MAR 20, 2012EDA Café: Testing Made Easy: Open Source VHDL Verification Methodology
MAR 13, 2012Electronics Weekly: FPGA Verification for DO-254 is in the Hardware
MAR 12, 2012Aldec Takes FPGA & ASIC Debugging to the Next Level
MAR 12, 2012Electronics Weekly: Aldec Design Tool Supports UVM and new SystemVerilog
FEB 29, 2012Aldec Launches DO-254 Practitioner’s Course with FAA DER, Randall Fulton
FEB 20, 2012Aldec to Address Biggest Safety and Mission-Critical Verification Challenges in Electronic Warfare at EWCI in India
JAN 23, 2012Aldec adds Documentation for Safety-Critical Designs in ALINT™ 2012.01
JAN 19, 2012Q1-2012 - Aldec™ Design and Verification Newsletter
JAN 13, 2012Verification Engineers are Invited to Take a Brief Survey and Receive a Chance to win an Ipad2!
JAN 09, 2012Aldec and SynthWorks deliver Randomization and Functional Coverage Capabilities to VHDL Designers with OS-VVM™
NOV 14, 2011Aldec Delivers Complete Support for UVM 1.1, Enabling VMM and OVM Interoperability
OCT 31, 2011Aldec Releases Active-HDL 9.1 Supporting Simulation of the Newest FPGA Devices
OCT 18, 2011Aldec presents ‘Automated Code Reviews for Fail-Safe Designs’ at ReSpace/MAPLD 2011 Conference in Albuquerque, NM.
OCT 18, 2011Aldec presents 'FPGA Level In-Hardware Verification for DO-254 Compliance' at the 30th Annual DASC in Washington
OCT 16, 2011IEEE: FPGA Level In-Hardware Verification for DO-254 Compliance
OCT 06, 2011Aldec Confirms Platinum Sponsorship of 9th Annual International System-on-Chip (SoC) Conference
OCT 06, 2011Q4-2011 - Aldec™ Design and Verification Newsletter
SEP 14, 2011Aldec Honored for Superior FPGA Design and Verification tools
SEP 13, 2011Aldec and Agnisys Partner to offer Closed Loop Verification Management to meet challenges in Verification of Modern Designs
SEP 12, 2011Randall Fulton, FAA Consultant DER, to present DO-254 Training Seminar hosted by Aldec in Las Vegas, NV
AUG 03, 2011Functional Verification Survey Winners
JUL 25, 2011Aldec’s Emulation and Verification Tools Adopted by UC San Diego for the new Master’s Program in Wireless Embedded Systems
JUL 21, 2011Q3-2011 - Aldec™ Design and Verification Newsletter
JUL 11, 2011Aldec Adds UVM Transaction-Level Visual Debugging
JUL 07, 2011Design your own Functional Verification Tool
JAN 13, 2011Q1-2011 - Aldec™ Design and Verification Newsletter
SEP 22, 2008Aldec selected by Thales to deploy DO-254/ED-80 CTS for Level B Certification Compliance of Advanced Avionics System
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