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DVCon Europe “must see”: Aldec tutorial and demonstration on adopting Easier UVM to enable FPGA-based Acceleration

Date: Nov 4, 2015Type: Release

Munich, Germany – November 5, 2015 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, is supporting the second Annual DVCon Europe conference taking place in Munich on Nov 11th and 12th. Not only have Aldec been chosen to present a technical tutorial on UVM acceleration but they are also showing live demonstrations at the conference exhibition of hardware-assisted verification of UVM following Doulos Ltd.’s Easier UVM guidelines. John Aynsley, Chief Technology Officer of Doulos and pioneer of the UVM standard, says “I am happy that Aldec endorses our Easier UVM approach as an excellent starting point and learning aid.”

The 90-minute tutorial focusses on the use of Easier UVM and SCE-MI to help teams get started with UVM and, importantly, to future-proof their UVM verification environments by making them acceleration-ready right from the start. Given the growth of FPGA-based emulation, simulation acceleration is becoming widely adopted, so the tutorial is timely in explaining that by being ready for acceleration, even late adopters of UVM can be early for the next wave of mainstream emulation.

Aldec verification expert, Alex Grove will give a real-world example of the use of Easier UVM, following on from an introduction by Doulos earlier in the DVCon conference. “Many verification teams may be familiar with the potential benefits of FPGA-based Verification” says Grove, “however, there is little material on how to harness FPGAs into mainstream verification methodology such as UVM; our tutorial aims to fill that gap”. Krzysztof “Chris” Szczur, co-author of the tutorial adds “in the tutorial, Alex will explain a UVM test environment that is acceleration-ready through the use of the Accellera SCE-MI standard and Easier UVM. Delegates will learn how this approach allows tests to be run in simulation and then accelerated on an FPGA Co-emulator through use of Aldec’s SCE-MI compiler.”

The adoption of UVM in Europe is patchy, with many verification teams yet to overcome barriers to adoption such as the learning curve and the need for greater simulation throughput. Obviously, Easier UVM code generator and guidelines can help with the learning curve but Aldec engineers have also adopted the Easier UVM for their own internal use; allowing faster and more accurate creation of accelerator-ready Verification IP. Aldec will demonstrate the fruits of this approach at their exhibition booth during DVCon, and will feature Riviera Pro simulation and the HES-DVM co-emulation solution.

Aldec are enthusiastic supporters of the new DVCon Europe conference. “It is important that European verification teams harness the benefits of the latest tools and methodology, including UVM”, says Mirek Marciniszyn, Aldec’s Executive Director of Operations. “We strongly support the establishment and growth of DVCon Europe and wish it every success in its second year”.

 

To attend the Easier UVM tutorials by Aldec and Doulos, attendees must register as DVCon Europe delegates (fee payable); see http://dvcon-europe.org/registration for details.

To learn more about UVM and the Easier UVM guidelines and code generator from Doulos, see http://www.doulos.com/knowhow/sysverilog/uvm/

 

About Aldec Hardware Emulation Solutions (HES)

HES-7™ provides SoC/ASIC hardware verification and software validation teams with a high-performance, scalable, and multi-purpose FPGA-based platform. HES-7, including HES-DVM, is used in labs worldwide for tasks including simulation acceleration, emulation, hybrid virtual prototypes, co-emulation, high-speed prototyping, and software validation at MHz speeds. Learn more about Aldec Hardware Emulation Solutions.

 

About Aldec

Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Emulation, Design Rule Checking, Clock Domain Crossing, VIP Transactors, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com

 


Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are the property of their respective owners.

Media Contact: Aldec, Inc.                               
Christina Toole, Corporate Marketing Manager
+ (702) 990-4400
christinat@aldec.com
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