Aldec Introduces SCE-MI Pipes-based Flow for Streaming High-volume Data and 30% Speed Increase with Latest Release of HES-DVM
Henderson, Nev. – March 15, 2016 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, today announces the latest release of HES-DVM™ 2016.01 software package for emulation and simulation acceleration on HES-7™ and custom, in-house high speed prototyping boards. The latest release of HES-DVM delivers significant improvement to supported SCE-MI emulation modes. Users will benefit from a newly introduced SCE-MI Pipes-based flow, targeted for streaming large amounts of data, and a 30% speed increase for all emulation modes due to the latest optimizations of the emulation engine and infrastructure.
“The increasing popularity of emulation solutions, particularly for UVM acceleration, generates the demand for simplicity of the emulator integration and reuse of the existing simulation testbench,” said Zibi Zalewski, General Manager of Aldec’s Hardware Division. “Our response is the support of SCE-MI Pipes-based mode with the benefits of SystemVerilog API; fast development of streaming transactors and the natural extension of already supported SCE-MI Function-based. In addition, the latest changes of the emulator architecture allow for even faster emulation runs with a shorter setup process thanks to our newly added automatic placement of partitions for guided partitioning.”
HES-DVM 2016.01 is ready for current customers and for evaluation. Existing customers with valid maintenance can request a software upgrade via the Aldec Support Portal. To learn more or to evaluate, please contact firstname.lastname@example.org or call us at (702) 990-4400 or via our worldwide distribution partners.
HES-DVM™ is a fully automated and scalable hybrid verification environment for SoC and ASIC designs. Utilizing the latest co-emulation standards like SCE-MI or TLM and the newest FPGA technology, hardware and software design teams obtain early access to the hardware prototype of the design. HES-DVM is used in labs worldwide for tasks including simulation acceleration, emulation, hybrid virtual prototypes, co-emulation, in circuit emulation, and software validation at MHz speeds. Learn more about Aldec Hardware Emulation Solutions.
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com
Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are the property of their respective owners.
|Media Contact:||Aldec, Inc.
Christina Toole, Corporate Marketing Manager
+ (702) 990-4400