Aldec Enhances Award-Winning Active-HDL with Flexible File Management to Manage Complex FPGA Projects

Date: Sep 24, 2012Type: Release

Henderson, NV – September 24, 2012 – Aldec, Inc. today announced the immediate availability of Active-HDL™ 9.2, an HDL-based FPGA Design and Simulation solution now offering flexible file management to allow engineers to effortlessly manage complex FPGA projects. This powerful concept enables designers to create project structures compatible with FPGA synthesis and place and route tools – allowing one common project structure to be used between multiple vendor tools. Team-based design features are also interwoven with the new file management feature to allow the design environment to be set up quickly, even when team members work from multiple locations.


“Active-HDL supports FPGA devices from Altera®, Atmel®, Lattice®, Microsemi® (Actel), Tabula®, QuickLogic®, and Xilinx® among many others,” said Satyam Jani, Aldec Software Division Product Manager, “This release of Active-HDL will bring clarity to the FPGA design flow as we allow users to customize and manage the project structure around multiple vendor tools.”


Simulation Performance

Active-HDL continues to dominate the FPGA market with powerful simulation performance, debugging tools and language support for VHDL 2008 and SystemVerilog (Design). Continued simulation performance optimizations from release to release enable users to benefit from faster simulation as the size of FPGA designs continues to grow.


Awarded Top FPGA Solution in China

Active-HDL, an all-in-one tightly integrated solution offering design creation, documentation, code coverage and simulation, was awarded the 2012 top FPGA Design, Verification and Simulation Platform for the third consecutive year by Chinese Electronics News (CEN)  and continues to be the tool of choice for FPGA designers.


Superior Automation

As more designs are reused, Active-HDL now offers a powerful Net-Optimizer feature that allows the auto-routing of nets with the block diagram editor and removes all redundant net segments to deliver cleaner designs for documentation and visualization.  Active-HDL 9.2 also introduces Mouse Gestures to improve the productivity of designers by enabling the execution of common tasks with a simple movement of the mouse.


For additional information about Active-HDL 9.2 including a What’s New presentation, Resources, and free Evaluation Download, visit www.aldec.com/Products/Active-HDL. Popular Active-HDL videos are also available at www.youtube.com/user/aldecinc.

Customers with a current maintenance contract are eligible to update to the latest release at no cost. New customers and customers without current maintenance contracts are invited to contact a local Aldec Distributor for more information.


About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com


Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.

Media Contact: Christina Toole,
Aldec, Inc.
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