ALINT-PRO™ | Design Rule Checking

Static Design Verification

ALINT-PRO™ is a design verification solution for RTL code written in VHDL, Verilog and SystemVerilog, which is focused on general issues analysis including: RTL and post-synthesis simulation mismatches, design coding for optimal synthesis, avoiding problems on further design stages, and coding for portability and reuse.

The solution performs static analysis based on RTL and SDC™ source files uncovering critical design issues early in the design cycle, which in turn reduces design signoff time dramatically. Running ALINT-PRO before the RTL simulation and logic synthesis phases prevents design issues spreading into the downstream stages of design flow and reduces the number of iterations required to finish the design.

ALINT-PRO features well-designed, intuitive framework, which offers features for efficient design analysis including schematic viewer, clocks and resets viewer, elaboration viewer and special tools such as chip control viewer for clock domain crossings analysis.

Setting up an existing HDL design for analysis in ALINT-PRO is supported with reading the external project file formats (Aldec Active-HDL, Aldec Riviera-PRO, Xilinx Vivado, Xilinx ISE, Altera Quartus), interpreting typical simulation scripts (compatibility commands like vcom, vlog, vsim, vlib), traditional file lists for the batch-mode tools, and very simple GUI wizards for direct import of individual files and whole directories.

ALINT-PRO smoothly supports running the rule checks for designs that target FPGA implementation using Xilinx, Altera, Microsemi and Lattice technologies with minimal setup. ALINT-PRO offers the latest versions of FPGA vendor libraries, which are pre-built, installed by default and optimized for advanced design rule checks

Key ALINT-PRO functions are also accessible via rich set of TCL-based scripting commands. The scripts can be used to automate design rule checks, repetitive settings and reports generation. The scripts can run in interactive console shell or in fully automatic batch mode.

Available Rule Libraries for ALINT-PRO™

ALINT-PRO includes rule libraries based on STARC (Semiconductor Technology Academic Research Center) design guidelines, which utilizes best practices in design developing used by semiconductor companies all over the world.

For safety critical designs, Aldec delivers rule libraries based on DO-254 guidelines focused on critical issues analysis that impact design stability.

The ALDEC_CDC rule plug-in turns ALINT-PRO into a full-scale CDC Verification solution capable of complex clock domain crossings analysis and handling of metastability issues in modern multi-clock designs. The verification strategy in ALINT-PRO is comprised from three key elements: static structural verification, design constraints setup, and dynamic functional verification. The first two steps are executed in ALINT-PRO, while dynamic checks are implemented via integration with simulators (Riviera-PRO™ , Active-HDL™, and ModelSim® are supported) based on the automatically generated testbench. This approach reveals potential CDC problems during RTL simulation, which otherwise would require lab tests to be detected. 

Top Features

  • Clock and Reset Networks Analysis
  • Avoiding post RTL and post Synthesis Simulation Mismatches
  • Code Portability and Reuse
  • Extensive CDC checks with ALDEC_CDC rule plug-in
  • Advanced CDC Debugging Environment
  • Schematic Viewer
  • DFT Checks
  • SDC™ Support
  • Design Constraints Extension for IP Description
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