ALINT-PRO™ | Design Rule Checking

Static Design Verification

ALINT-PRO™ is a design verification solution for RTL code written in VHDL, Verilog, and SystemVerilog, which is focused on verifying coding style and naming conventions, RTL and post-synthesis simulation mismatches, smooth and optimal synthesis, avoiding problems on further design stages, clocks and reset tree issues, CDC, DFT, and coding for portability and reuse. The solution performs static analysis based on RTL and SDC™ source files uncovering critical design issues early in the design cycle, which in turn reduces design signoff time dramatically. Running ALINT-PRO before the RTL simulation and logic synthesis phases prevents design issues spreading into the downstream stages of design flow and reduces the number of iterations required to finish the design.


Single Framework for DRC and CDC Analysis

ALINT-PRO features a well-designed, intuitive framework, which offers features for efficient design analysis including RTL schematic viewer, clocks and resets viewer, control schematics viewer, elaboration viewer, violation viewer, and special tools such as CDC viewer and CDC schematics for clock domain crossings analysis.


Setting up an existing HDL design for analysis in ALINT-PRO is supported by reading external project file formats (Aldec Active-HDL, Aldec Riviera-PRO, Xilinx Vivado, Xilinx ISE, Intel Quartus), interpreting typical simulation scripts (compatibility commands like vcom, vlog, vsim, vlib) as well as traditional file lists for the batch-mode tools, and very simple GUI wizards for direct import of individual files and whole directories.


FPGA Vendors Support

ALINT-PRO smoothly supports running the rule checks for designs that target FPGA implementation using Xilinx, Altera, Microsemi, and Lattice technologies with minimal setup. ALINT-PRO offers the latest versions of FPGA vendor libraries, which are pre-built, installed by default, and pre-configured for advanced timing and CDC rule checks.


Batch Mode Flows

Key ALINT-PRO functions are also accessible via a rich set of TCL-based scripting commands. The scripts can be used to automate design rule checks, repetitive settings, and reports generation. The scripts can run in interactive console shell or in fully automatic batch mode. ALINT-PRO provides command-line based entry points for background running in external HDL editors, which shortens the interval between making and eliminating coding mistake from hours to minutes and seconds, enabling an uninterrupted verification loop while editing the RTL. Finally, ALINT-PRO is capable of running the most typical design entry and linting scenario in true batch mode using a single command-line shell application call, which makes it perfectly suitable to integrate with larger regression testing scripting and continuous integration environments.


Available Rule Libraries for ALINT-PRO™

ALINT-PRO includes rule libraries based on STARC (Semiconductor Technology Academic Research Center) and RMM (Reuse Methodology Manual) design guidelines, which utilizes best practices in design development used by semiconductor companies all over the world. For safety critical designs, Aldec delivers rule libraries based on DO-254 guidelines focused on critical issues analysis that impact design stability.


The main rule plugins are complemented with highly configurable Aldec Basic and Premium rule libraries, which are driven by Aldec in-house experience with FPGA and ASIC digital design, as well as include many additions recommended by existing ALINT-PRO customers, fighting against chip killer issues in industrial-scale designs.  ALDEC SV plugin targets new varieties of RTL mistakes specific to SystemVerilog design subsets.


The ALDEC_CDC rule plug-in turns ALINT-PRO into a full-scale CDC Verification solution capable of complex clock domain crossings analysis and handling of metastability issues in modern multi-clock designs. The verification strategy in ALINT-PRO is comprised from three key elements: static structural verification, design constraints setup, and dynamic functional verification. The first two steps are executed in ALINT-PRO, while dynamic checks are implemented via integration with simulators (Riviera-PRO™ , Active-HDL™, and ModelSim® are supported) based on the automatically generated testbench. This approach reveals potential CDC problems during RTL simulation, which otherwise would require lab tests to be detected. Debugging CDC issues is being achieved via rich schematic and HDE cross-probing mechanisms, as well as comprehensive reports and TCL-based API, which allows browsing through the synthesis results, clocks and resets structures, detected clock domain crossings, and identified synchronizers.


Top Features

  • Clock and Reset Networks Analysis
  • Avoiding post RTL and post Synthesis Simulation Mismatches
  • Code Portability and Reuse
  • Extensive CDC checks with ALDEC_CDC rule plug-in
  • Advanced CDC Debugging Environment
  • Schematic Viewer
  • DFT Checks
  • SDC™ Support
  • Design Constraints Extension for IP Description
  • Background and batch running modes
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