Aldec Presents at Military & Aerospace Programmable Logic Devices Symposium (MAPLD)

Date: Apr 8, 2013
Type: Release

Henderson, NV – April 8, 2013 – Aldec, Inc. together with Microsemi, The Boeing Company, Northrop Grumman Corporation and other leading vendors, is scheduled to present at the Military and  Aerospace Programmable Logic Devices Symposium (MAPLD) in San Diego, CA from April 9-12, 2013.

MAPLD event will showcase leading research in the field of programmable devices for use in military and aerospace applications. Aldec will present on two separate Design and Verification topics that continue to provide a high level of interest from the military and aerospace community. 


UVM Made Easy - High-level Verification for Hardware Designers    
Abstract: Discusses the general structure of UVM test environment and quickly proceeds to transactions and packets – key data structures used in TLM. Sequencers, drivers and monitors (components processing transactions and packets) are introduced with special attention paid to the concept of ‘virtual interface’ that creates a bridge between UVM internals and the tested design. The presentation concludes with the discussion of UVM components responsible for data analysis and wrapping everything together in UVM Environment. Methods of configuring test environment from the top-level module are also presented.

Hybrid Platform for High Capacity FPGA Validation and Verification
Abstract: As design size and system complexity continue to increase with the evolution of high capacity field programmable gate arrays (FPGAs), the verification stage grows more crucial to development teams. Today’s military and defense sectors require a properly verified and validated design, before deployment into field implementation. System designs consisting of multi-million gate FPGA’s may require billions of test cycles equating to hours or maybe even days of register transfer level (RTL) simulation. Simulators alone simply cannot tackle the tasks needed by both hardware designers and verification engineers.

MAPLD organizers will offer recorded podcasts of the technical sessions, available to download following the symposium for a fee or at no cost to registered attendees.



This year, MAPLD joins the Single-Event Effects (SEE) Symposium which addresses all aspects of single-event effects (SEE) in microelectronic and photonic devices, circuits, and systems. Military and Aerospace Programmable Logic Devices presentations will explore the use of programmable devices for use in military and aerospace with an emphasis of proper operation in extreme conditions at high altitude and in space. SEE/MAPLD also includes a combined industrial exhibition.


About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions.

Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.

Media Contact: Christina Toole, Aldec, Inc.
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