Recent NewsAldec to Showcase FPGA Acceleration of Genome Alignment, Motion Detection and Face Detection Algorithms at isFPGA 2017 Release FEB 21, 2017 Aldec sets a new paradigm with a single platform for Design Rule Checking and Clock Domain Crossing Verification for FPGA and ASIC designs Release FEB 14, 2017 Aldec delivers DO-254 Compliant Templates and Checklists with the latest release of Spec-TRACER Release FEB 01, 2017 Aldec provides Finite State Machine Coverage for verification of safety-critical FPGAs Release JAN 19, 2017 Top Aldec Design and Verification Blog Articles from 2016 Release DEC 07, 2016 Aldec delivers significant SystemVerilog speedup and a pioneering initiative for VHDL users with latest Riviera-PRO Release NOV 16, 2016 Aldec and Indian Institute of Science faculty enterprise, ReneLife, showcase ReneGENE for accurate genome alignment on HES Accelerator at SC16 Release NOV 14, 2016 SemiWiki: 3 in 1 Hardware Verification In the News NOV 14, 2016 Aldec adds largest Xilinx UltraScale to latest HES Solution for FPGA Simulation Acceleration, Emulation, and Prototyping to be unveiled at SemIsrael 2016 Release NOV 10, 2016 Semiconductor Engineering: Emulation’s Footprint Grows In the News OCT 27, 2016
Recent Blog Articles
ALINT-PRO 2017.01 is now released
For most scientists, what is inside a high-performance computing platform is a mystery.
How can we do this faster and with better quality - at no extra cost?
My thoughts after DVCon Europe
In-depth Overview of VDMA Use Cases for TySOM™ Reference Designs
Industry Event Monterey, California FEB 22, 2017
Training Tokyo, Japan FEB 23, 2017
Industry Event San Jose, California FEB 27, 2017
Industry Event Nürnberg, Germany MAR 14, 2017