Recent NewsAldec Celebrates 10 Years in DO-254 at Certification Together International Conference Release MAR 15, 2017 Aldec Introduces End-to-end HW/SW Co-verification for Xilinx Zynq SoC FPGAs at Embedded World 2017 Release MAR 07, 2017 Aldec unveils Xilinx UltraScale FPGA-based prototyping board enabling Simulation Acceleration and Emulation with the latest release of HES-DVM Release FEB 28, 2017 Aldec to Demonstrate UVM Simulation Acceleration with Network-On-Chip (NoC) Demo Design at DVCon U.S. 2017 Release FEB 23, 2017 Aldec to Showcase FPGA Acceleration of Genome Alignment, Motion Detection and Face Detection Algorithms at isFPGA 2017 Release FEB 21, 2017 Aldec sets a new paradigm with a single platform for Design Rule Checking and Clock Domain Crossing Verification for FPGA and ASIC designs Release FEB 14, 2017 Aldec delivers DO-254 Compliant Templates and Checklists with the latest release of Spec-TRACER Release FEB 01, 2017 Aldec provides Finite State Machine Coverage for verification of safety-critical FPGAs Release JAN 19, 2017 Top Aldec Design and Verification Blog Articles from 2016 Release DEC 07, 2016 Aldec delivers significant SystemVerilog speedup and a pioneering initiative for VHDL users with latest Riviera-PRO Release NOV 16, 2016
Recent Blog Articles
ALINT-PRO 2017.01 is now released
For most scientists, what is inside a high-performance computing platform is a mystery.
How can we do this faster and with better quality - at no extra cost?
My thoughts after DVCon Europe
In-depth Overview of VDMA Use Cases for TySOM™ Reference Designs
Training Tokyo, Japan MAR 29, 2017
Training Tokyo, Japan APR 07, 2017
Training Tokyo, Japan APR 13, 2017
Training Tokyo, Japan APR 19, 2017