Recent NewsAldec to Demonstrate Design Verification Techniques with Hardware-In-The-Loop and QEMU at DvCON China 2017 Release APR 17, 2017 Aldec continues to stack up pre-compiled verification libraries and delivers significant SystemVerilog and UVM speedup with latest release of Riviera-PRO Release APR 11, 2017 Aldec Celebrates 10 Years in DO-254 at Certification Together International Conference Release MAR 15, 2017 Aldec Introduces End-to-end HW/SW Co-verification for Xilinx Zynq SoC FPGAs at Embedded World 2017 Release MAR 07, 2017 Aldec unveils Xilinx UltraScale FPGA-based prototyping board enabling Simulation Acceleration and Emulation with the latest release of HES-DVM Release FEB 28, 2017 Aldec to Demonstrate UVM Simulation Acceleration with Network-On-Chip (NoC) Demo Design at DVCon U.S. 2017 Release FEB 23, 2017 Aldec to Showcase FPGA Acceleration of Genome Alignment, Motion Detection and Face Detection Algorithms at isFPGA 2017 Release FEB 21, 2017 Aldec sets a new paradigm with a single platform for Design Rule Checking and Clock Domain Crossing Verification for FPGA and ASIC designs Release FEB 14, 2017 Aldec delivers DO-254 Compliant Templates and Checklists with the latest release of Spec-TRACER Release FEB 01, 2017 Aldec provides Finite State Machine Coverage for verification of safety-critical FPGAs Release JAN 19, 2017
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Industry Event Santa Clara, California MAY 01, 2017
Training Taipei, Taiwan MAY 09, 2017
Training Taipei, Taiwan MAY 11, 2017
Training Online MAY 12, 2017