Aldec Design and Verification Blog

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SystemVerilog Functional Coverage in a Nutshell
Use native SystemVerilog constructs as metrics for verification closure in Riviera-PRO

Let’s say you have a block you need to verify. How do you know that the stimulus you are about to use is exhaustive enough and that you have covered the necessary scenarios/situations to prove it is working correctly?...

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Trace Your Assertions

When I enter the word “assertions” into a search engine I get lots of results, including articles, books, courses, and tools. Nothing unusual there, as assertions have been present in the EDA industry for many years. They considerably increase...

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Unit Linting: An easy way to prevent code review issues

Code reviews, aren’t they a pain? Every time you have to go through one, you find yourself thinking: “Why oh why I didn’t fix this thing in the beginning? It’ just a small formatting issue, but there are 100 files that have the same issue. I forgot to add comments to the state machines and I did not label my processes”. ...

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How to develop an FPGA-based Embedded Vision application for ADAS, series of blogs – Part 1
FPGA “The winner for the low-power and high-performance vision-based applications”

When should we use the term “Vision for Everything”, as vision-based applications are entering various industries? It’s been a few years since the emergence of...

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Understanding the inner workings of UVM - Part 2
UVM Basics Part 2 of 3

In this blog, my major focus is on explaining the concepts such as Sequence, Sequencer, Driver and showing how the communication takes place from sequence to sequencer and from sequencer to driver. In the previous blog, I included...

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How to Design the New Generation of Reprogrammable Router/Switch Using Zynq FPGA
A must for high-traffic network

A high-performance router is an absolute must if you want to run a high-traffic network in which different devices need to transfer and receive data as fast as possible. A router with a powerful processor and sufficient local memory...

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Partition your Design for FPGA Prototyping
Easily create partitions with HES-DVM

Modern ASIC and SoC designs have increased in complexity such that multiple FPGAs of the largest capacity are now required to prototype the entire functionality of the design. As design sizes increase, more and more...

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Plots: A New Way To Analyze Data

Data analysis is often a very time consuming process for a hardware design or verification engineer. We always end up using the waveform viewer which may not be very efficient in giving us a high-level overview of what we’re looking for. Data that is spread across...

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Emulation in FPGA

For many years, emulators were available only to verification teams working on the largest projects in companies with deep enough pockets. Due to size rather than capabilities they were called “Big Box” emulators and typically were used in order to recover...

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Code Coverage in HDL Editor? Now That’s a Nice Feature.

For a long time I have been a fan of code coverage tools that are embedded into the simulators themselves, and which give you the ability to switch easily between the code and the coverage results. It is particularly helpful to have a way...

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