Aldec Design and Verification Blog

Trending Articles
Code Coverage – Can we get a little help here?
Productivity boost from Condition and Path Coverage

Don’t get me wrong, coverage analysis has been used by engineers for years now and it usefulness in improving productivity and verification environment quality can’t be stressed enough....

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Extend Vivado Capabilities with Help From the Tcl Store
Xilinx Vivado Tutorial: Upgrade for increased simulation performance

Outgrowing something can be hard. So hard, that sometimes we live in denial longer than we should. We are resistant to change, often because we are simply too comfortable with what we know (or too busy) to consider the options....

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DO-254 Book: Airborne Electronic Hardware Design Assurance
An interview with Randall Fulton

I recently interviewed Randall Fulton, one of the authors of the popular DO-254 book “Airborne Electronic Hardware Design Assurance”. This book is the extension of the 3-day DO-254 Practitioner’s Course we conduct together annually as partners....

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FPGAs Cross Scale Threshold to Enable True FPGA-based Verification
Guest Blog by Doug Amos, One-Man-Army FPGA Consultant

See full version of this article on EETimes. The news is out! Aldec is adopting Xilinx® Virtex® UltraScale™ devices in its seventh generation Hardware Emulation Solution, HES-7™, heralding a great leap in the capability of FPGA-based verification....

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Putting the “Automation” back into EDA
The Pythonic Tonic: Miracle cure or Snake-oil?

There are plenty of buzzwords floating around in EDA right now - wherever you go people are talking about agile, portable stimulus or "shift-left". We attend conferences and listen to representatives from the best companies in the world...

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So, what does a vendor-independent simulator look like?
Tackle your next FPGA design with Active-HDL ™

Well, the short answer to that is, “Awesome”. Perhaps, as the product manager of a simulation tool, I’m a little biased. Not to discount the challenges that FPGA design teams face on daily basis,...

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How can Verification IPs Help the SoC Testing Process?
How to use VIPs In Practice

Let’s assume that we are designing a new system on chip (SoC) which contains a processor and memory controller, as well as analog and digital peripherals like Ethernet, USB, 1-Wire and JTAG controllers....

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How to Properly Verify Encrypted IP
Using Block Level Constraints for Description of Non-Synthesizable Design Units

FPGA vendors typically provide a set of various IPs which cannot be directly used for synthesis. Although these components are fully tested by the vendor, verifying the design that uses them can become a tricky task within some linting tools....

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Save hours of Place & Route time… in seconds
Vivado Incremental Compile for faster Emulation Setup

Place & Route implementation can sometimes feel like it takes forever. Consider some of these common scenarios:   ● After working overtime to create an emulation build for all emulation users, your manager brings you some...

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Are Metastability Monsters Lurking Beneath the Surface?
Taming Clock Domain Crossing Issues with ALINT-PRO-CDC™

Every engineer and technician is aware of Murphy’s Law: “Anything that can go wrong will go wrong”. The law appears when your elegantly-sculpted hardware and artfully-styled software code bang up against the real world...

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