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Aldec Design and Verification Blog

Trending Articles
How can Verification IPs Help the SoC Testing Process?
How to use VIPs In Practice

Let’s assume that we are designing a new system on chip (SoC) which contains a processor and memory controller, as well as analog and digital peripherals like Ethernet, USB, 1-Wire and JTAG controllers....

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How to Properly Verify Encrypted IP
Using Block Level Constraints for Description of Non-Synthesizable Design Units

FPGA vendors typically provide a set of various IPs which cannot be directly used for synthesis. Although these components are fully tested by the vendor, verifying the design that uses them can become a tricky task within some linting tools....

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Save hours of Place & Route time… in seconds
Vivado Incremental Compile for faster Emulation Setup

Place & Route implementation can sometimes feel like it takes forever. Consider some of these common scenarios:   ● After working overtime to create an emulation build for all emulation users, your manager brings you some...

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Are Metastability Monsters Lurking Beneath the Surface?
Taming Clock Domain Crossing Issues with ALINT-PRO-CDC™

Every engineer and technician is aware of Murphy’s Law: “Anything that can go wrong will go wrong”. The law appears when your elegantly-sculpted hardware and artfully-styled software code bang up against the real world...

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Xilinx Tcl Store Integrates Aldec Simulators with Vivado IDE
App now integrates Active-HDL & Riviera-PRO

Taking a cue from the open-source community, Xilinx has launched a Tcl Store that aggregates Tcl scripts contributed by the greater development community to expand the capabilities of the Vivado® Integrated Design Environment....

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What inspired you to become an engineer?
National Engineering Week is February 22-28

This week, February 22-28, we celebrate National Engineers Week in the US to recognize the contributions to society that engineers make. During this time, there is added emphasis in schools on the importance of learning...

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It’s Here! ALINT-PRO-CDC™ for CDC Verification
Aldec’s new solution for complex multi-clock designs

I am happy to announce, that today Aldec has released ALINT-PRO-CDC™ 2015.01. This solution enables verification of clock domain crossings and handling of metastability issues in complex, modern multi-clock designs....

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Transitioning to Advanced Verification Techniques for FPGAs – Catch-22?
A Guest Blog by TVS Founder and CEO, Dr. Mike Bartley

Many FPGA designers find themselves in a catch-22: they recognise that their designs are becoming too complex for their current verification strategies BUT adopting advanced verification techniques (such as the Universal Verification Methodology – UVM) is...

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Useful resources to help you get ahead

“USEFUL” is a word you’ll hear a lot over here at Aldec. It’s the number one way we rank our success when developing a new product or feature. “How USEFUL is it?” is the most common phrase we challenge one another...

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Scaling the “Internet of Things”
With Aldec HES-DVM™

Happy New Year! January brought an unseasonably warm wave of weather to Las Vegas as International CES converged on the city this month. The size and scope of this worldwide consumer electronics tradeshow...

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