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The Race to Zero Latency for High Frequency Trading

The High-Frequency Trading (HFT) industry has received a lot of attention during the last few years. HFT is all about speed and minimizing latency: the faster you can run trading strategies and algorithms for analyzing minute price changes...

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FPGA vs GPU for Machine Learning Applications: Which one is better?
Can FPGAs beat GPUs?

FPGAs or GPUs, that is the question.   Since the popularity of using machine learning algorithms to extract and process the information from raw data, it has been a race between FPGA and GPU vendors to offer...

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Verification Effectiveness with Riviera-PRO: SystemVerilog Randomized Layered Testbench
Understanding SystemVerilog Layered Testbench

In this blog, I will discuss randomized layered testbenches used in SystemVerilog. We need to understand why we need it, ...

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Do I really need a commercial simulator?
A quick view of the benefits of a commercial simulator

As an Applications Engineer I visit lots of potential customers, or talk to them at trade shows, who are doing FPGA designs but don’t own a commercial simulator. I ask them why that is. Most of the time it is budgetary restrictions. They don’t...

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Understanding the inner workings of UVM - Part 3
UVM Basics Part 3 of 3

In this blog, I am going to discuss different phases that UVM follows.   The reason why UVM came up with such phases is because synchronization among all design-testbench was necessary. Using Verilog and VHDL,...

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SystemVerilog Functional Coverage in a Nutshell
Use native SystemVerilog constructs as metrics for verification closure in Riviera-PRO

Let’s say you have a block you need to verify. How do you know that the stimulus you are about to use is exhaustive enough and that you have covered the necessary scenarios/situations to prove it is working correctly?...

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Trace Your Assertions

When I enter the word “assertions” into a search engine I get lots of results, including articles, books, courses, and tools. Nothing unusual there, as assertions have been present in the EDA industry for many years. They considerably increase...

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Unit Linting: An easy way to prevent code review issues

Code reviews, aren’t they a pain? Every time you have to go through one, you find yourself thinking: “Why oh why I didn’t fix this thing in the beginning? It’ just a small formatting issue, but there are 100 files that have the same issue. I forgot to add comments to the state machines and I did not label my processes”. ...

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How to develop an FPGA-based Embedded Vision application for ADAS, series of blogs – Part 1
FPGA “The winner for the low-power and high-performance vision-based applications”

When should we use the term “Vision for Everything”, as vision-based applications are entering various industries? It’s been a few years since the emergence of...

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Understanding the inner workings of UVM - Part 2
UVM Basics Part 2 of 3

In this blog, my major focus is on explaining the concepts such as Sequence, Sequencer, Driver and showing how the communication takes place from sequence to sequencer and from sequencer to driver. In the previous blog, I included...

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