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Vegetarian Dining in Austin - DAC 2016
Helpful Tips From a Local

I moved to Austin a little over a year ago, and have quickly learned that this city is a progressive blue island in a sea of red. That's the conventional wisdom, and most of the time it holds up....

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The UVM Configuration Database
Keeping a neat repository for flexible testbench structure

When I want to wear a certain clothing item, I take out it of the closet. When I go shopping, I add those clothes it to my closet and there are now new items for me to pick out in the future....

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To Emulate or Prototype?
Is it even a question?

Recently I read a Semiwiki article, Army of Engineers on Site Only Masks Weakness, in which author Jean-Marie Brunet of Mentor Graphics wrote that FPGA Prototyping requires an army of tech support engineers on-site to mask...

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The hardest part of DO-254 is…
Insight from Aldec’s 3-Day DO-254 Practitioner’s Course

The hardest part of DO-254 is not the requirements. It’s not the design. It’s not the verification.   We just wrapped up this year’s 3-day DO-254 Practitioner’s Course, and each year I learn something new. In this year’s training we had attendees...

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Aldec Verification Tools Implement the ASIC Verification Flow
Insights from Dr. Stanley Hyduke, Aldec Founder and CEO

Aldec has, over the last 30 years, established itself as the preferred provider of high-performance, cost-effective verification tools for use in proving out complex FPGA designs. As the logic capacity and capability...

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Acceleration-Ready UVM
Guest Blog by Doulos CTO, John Aynsley

We hear that emulation is one of the fastest-growing segments in EDA right now, yet simulation still continues to be the main workhorse for functional verification, and SystemVerilog and UVM are everywhere you look....

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UVM Register Layer: The Structure
Creating an anatomically correct model for poking and prodding.

I don’t know about you, but I am looking forward to the day where we won’t even have to go to the doctor’s office for an exam. Instead, we will all have scanners in our homes that will transmit full digital models to our doctors...

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Why I see C in SCE-MI
A Hardware Emulation Guide for Non-C Designers

The two questions I hear most often while doing presentations about SCE-MI transaction based emulation are “Can we have coffee break?” and “Why do we need a thin C layer between two SystemVerilog tops”?...

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UVM. It’s Organized and Systematic.
Mastering the fundamentals

One of the reasons I like using UVM is its tendency toward an organized structure and uniformity. Some may find it annoying to adhere to such a strict format in UVM, but I think it’s a good way to keep the basics of UVM engrained in your brain....

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Reprogrammable, reprogrammable, reprogrammable: What’s great about FPGAs!
Guest Blog by Alex Grove, Applications Specialist at FirstEDA

I like FPGAs. My first experience with an FPGA was my university final year project where I demonstrated BIST with four Xilinx© 3000 devices; this was before FPGAs had JTAG built in. Filling up these devices...

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