Partners

Aldec Design and Verification Blog

Trending Articles
Acceleration-Ready UVM
Guest Blog by Doulos CTO, John Aynsley

We hear that emulation is one of the fastest-growing segments in EDA right now, yet simulation still continues to be the main workhorse for functional verification, and SystemVerilog and UVM are everywhere you look....

Like(0) Comments (0) Read more
UVM Register Layer: The Structure
Creating an anatomically correct model for poking and prodding.

I don’t know about you, but I am looking forward to the day where we won’t even have to go to the doctor’s office for an exam. Instead, we will all have scanners in our homes that will transmit full digital models to our doctors...

Like(1) Comments (0) Read more
Why I see C in SCE-MI
A Hardware Emulation Guide for Non-C Designers

The two questions I hear most often while doing presentations about SCE-MI transaction based emulation are “Can we have coffee break?” and “Why do we need a thin C layer between two SystemVerilog tops”?...

Like(2) Comments (0) Read more
UVM. It’s Organized and Systematic.
Mastering the fundamentals

One of the reasons I like using UVM is its tendency toward an organized structure and uniformity. Some may find it annoying to adhere to such a strict format in UVM, but I think it’s a good way to keep the basics of UVM engrained in your brain....

Like(1) Comments (0) Read more
Reprogrammable, reprogrammable, reprogrammable: What’s great about FPGAs!
Guest Blog by Alex Grove, Applications Specialist at FirstEDA

I like FPGAs. My first experience with an FPGA was my university final year project where I demonstrated BIST with four Xilinx© 3000 devices; this was before FPGAs had JTAG built in. Filling up these devices...

Like(1) Comments (0) Read more
Verifying Large FPGAs Isn't Easy
Guest Blog by Doug Perry, Senior Member Technical Staff at Doulos

The latest crop of FPGA devices are enormous when compared to ASICs that were built not that long ago. Verifying these ASICs required detailed plans, multiple tools, and sometimes special languages....

Like(0) Comments (0) Read more
U.V.M. Spells Relief
Create robust test environments with ease

Verification can be a challenging endeavor. As designs grow in size and complexity, engineers are having difficulty confirming their designs behave properly. This is where UVM may provide some relief....

Like(2) Comments (0) Read more
A Comprehensive RTL Verification Solution for VHDL
ALINT-PRO™ Design Rule Checking Solution

On Thursday, November 19, I’ll be hosting a webinar to demonstrate Aldec’s RTL Verification Solution for VHDL, ALINT-PRO™ Design Rule Checking Solution.   ALINT-PRO is Aldec’s design verification solution for RTL code...

Like(1) Comments (0) Read more
UVM Really is Everywhere
Guest Blog by Doulos CTO, John Aynsley

According to the official email newsletter sent out in advance of DVCon Europe 2015 in Munich, top of the list of topics for the tutorial day is "Basic UVM, advanced UVM, UVM reuse, all things UVM"....

Like(1) Comments (0) Read more
The Problem with CDCs
And how it affects your DO-254 project

Part of the Planning Process in DO-254 is knowing the appropriate FPGA tools and capabilities that you need and intend to use for your FPGA design. Particularly if your FPGA device...

Like(1) Comments (0) Read more
Ask Us a Question
x

Ask Us a Question

x
Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.