Aldec Design and Verification Blog

Trending Articles
Reprogrammable, reprogrammable, reprogrammable: What’s great about FPGAs!
Guest Blog by Alex Grove, Applications Specialist at FirstEDA

I like FPGAs. My first experience with an FPGA was my university final year project where I demonstrated BIST with four Xilinx© 3000 devices; this was before FPGAs had JTAG built in. Filling up these devices...

Like(0) Comments (0) Read more
Verifying Large FPGAs Isn't Easy
Guest Blog by Doug Perry, Senior Member Technical Staff at Doulos

The latest crop of FPGA devices are enormous when compared to ASICs that were built not that long ago. Verifying these ASICs required detailed plans, multiple tools, and sometimes special languages....

Like(0) Comments (0) Read more
U.V.M. Spells Relief
Create robust test environments with ease

Verification can be a challenging endeavor. As designs grow in size and complexity, engineers are having difficulty confirming their designs behave properly. This is where UVM may provide some relief....

Like(2) Comments (0) Read more
A Comprehensive RTL Verification Solution for VHDL
ALINT-PRO™ Design Rule Checking Solution

On Thursday, November 19, I’ll be hosting a webinar to demonstrate Aldec’s RTL Verification Solution for VHDL, ALINT-PRO™ Design Rule Checking Solution.   ALINT-PRO is Aldec’s design verification solution for RTL code...

Like(0) Comments (0) Read more
UVM Really is Everywhere
Guest Blog by Doulos CTO, John Aynsley

According to the official email newsletter sent out in advance of DVCon Europe 2015 in Munich, top of the list of topics for the tutorial day is "Basic UVM, advanced UVM, UVM reuse, all things UVM"....

Like(0) Comments (0) Read more
The Problem with CDCs
And how it affects your DO-254 project

Part of the Planning Process in DO-254 is knowing the appropriate FPGA tools and capabilities that you need and intend to use for your FPGA design. Particularly if your FPGA device...

Like(0) Comments (0) Read more
‘Don’t Be Afraid of UVM’ Webinar on YouTube
Free webinar from the Aldec archives

Just in time for Halloween, Aldec has released a popular past webinar Don’t be Afraid of UVM for Hardware Designers on YouTube. Designers are usually very busy doing their work and have little time left for experimentation...

Like(0) Comments (0) Read more
The Science of Verification
Boost your Verification Plan with Code Coverage

Science is a product of endless counts of trial and error. Without an error, how can we tell that something is right? This is the main reason why we perform verification....

Like(0) Comments (0) Read more
Emulation: Thinking outside of the Big Box
Guest Blog by Doug Amos, One-Man-Army FPGA Consultant

There’s no question; verification is a massive time drain in SoC and other chip design projects. For many years, those with deep enough pockets have turned to so-called “Big Box” emulators in order to recover some of the time lost on RTL simulation,...

Like(0) Comments (0) Read more
Helping FPGA Designers get started with UVM
Guest Blog by Doulos CTO, John Aynsley

UVM (the Universal Verification Methodology for SystemVerilog) represents best practice in constrained random functional verification, so it is something that every digital design and verification engineer should be aware of....

Like(0) Comments (0) Read more
Ask Us a Question

Ask Us a Question

Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.