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Accelerating Simulation of Vivado Designs with HES
Improve verification speedup with Aldec’s HES-DVM

FPGA Design Verification Challenge The FPGA design and verification “ecosystem” changes rapidly to keep pace with the fast growing size of FPGA devices. The largest Xilinx Virtex UltraSCALE chips provide 4.4 Million logic cells...

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Traceability Matrices: Headache or Real Value

Traceability is becoming increasingly important in most engineering projects, if only on the grounds of ‘good practice’, and it is specifically required for projects that have to meet safety standards such as DO-254 and ISO 26262....

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VHDL-2017: Some of My Favorite Things

For the past several years I have had the privilege to chair the IEEE 1076 VHDL working group. In March we handed off the revisions to the VHDL LRM to our technical editor to finalize the document for balloting. As we are waiting for the standards process to finish up, I thought I would share my favorite new additions. Let me start with an executive summary: ...

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Austin's Best Vegetarian Restaurants: The Quest Continues

If you’re headed to DAC, you should know it's fixing to be the hottest summer ever in Austin, but for brave and hungry meatless eaters, this town is an increasingly cool destination, with creative restauranteurs finding new ways to transform meaty favorites into plant-based edible delights....

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Emulation on the Cloud
HES Cloud delivers access to a high performance emulation platform

‘The cloud’ has been an industry buzz word for some time now and whilst the initial focus was on data storage and sharing - and spawned the likes of Dropbox – ‘cloud computing’ is currently the latest trend. For instance, Amazon’s cloud platform, ...

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FPGAs in an SoC World
How modern FPGA architecture influences verification methodologies

The SoC domination observed so far in the ASIC industry is coming to the FPGA world and changing the way FPGAs are used and FPGA projects are verified. The latest SoC FPGA devices  ...

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Aldec Springs Into Action
A look back at a busy industry show season

It’s been a busy season for Aldec. The weather has warmed here in the desert and as the trees and greenery enliven in spring, Aldec has also been bursting with activity. From DVCon to the International Symposium on FPGAs in the US to Embedded World ...

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Software Driven Test of FPGA Prototype
Use development software to drive your DUT on an FPGA prototyping platform

Most everyone would agree how important FPGA prototyping is to test and validate an IP, sub-system, or a complete SoC design. Before the design is taped-out it can be validated at speeds near real operating conditions with physical peripherals and devices connected to it instead of simulation models. ...

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Key Components of Effective RTL Linting and CDC Verification
Solving your challenges with ALINT-PRO

Automated design rule checking, or linting, has been around the RTL verification for at least a couple decades, still many HDL designers completely ignore this simple yet very powerful bug hunting method. Why would a busy designer need to run this annoying warning generator?...

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An Easier Path to Faster C with FPGAs
For most scientists, what is inside a high-performance computing platform is a mystery.

For most scientists, what is inside a high-performance computing platform is a mystery. All they usually want to know is that a platform will run an advanced algorithm thrown at it. ...

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