FirstEDA to introduce Aldec’s FPGA Co-emulator at Verification Futures Europe
Henderson, NV – February 2, 2016 – Aldec is a proud Gold Sponsor and presenter at Verification Futures 2016, a unique one day conference, exhibition and industry networking event organized by TVS. Scheduled to be held Thursday, February 4, 2016, in Reading, UK, Verification Futures is the largest dedicated ASIC and FPGA verification event in Europe.
Alex Grove, of Aldec Distributor, FirstEDA, is scheduled to present, ’Using FPGAs to accelerate verification of your next ASIC: Introducing the FPGA Co-emulator’. Alex is an expert on Aldec solutions with a particular focus on hardware-assisted verification and RTL simulation products. Below follows a brief abstract of his scheduled presentation.
Never has the need to accelerate verification been so great; reduced market windows, ever increasing complexity and a growing need for longer tests. Most ASIC IP and SoC platforms will be validated at some point using FPGAs; this task is typically known as ASIC FPGA prototyping. Such a prototype is the closest representation of the final silicon and typically used to validate and test software and perform at-speed testing of real world interfaces.
At the same time, FPGAs are increasingly being used for verification due to the performance and scalability of such systems. These systems are very different in their capabilities to that employed for ASIC FPGA prototyping. The use of FPGAs provides the greatest capability in terms of verification cycles and are ideal for regression. With the arrival of Xilinx’s UltraScale, the capability of FPGA-based verification has never been so great.
In this short presentation we will introduce the FPGA Co-emulator and discuss two typical use cases for such a system:
- The verification of hardware dependent software (HdS)
- UVM simulation acceleration
About Verification Futures
Verification Futures is organized by TVS to discuss the challenges faced in hardware verification. The event gives the opportunity for end users to define their current and future verification challenges and collaborate with the vendors to create solutions. It’s also an excellent opportunity to network and catch up with other verification engineers across Europe. Visit www.testandverification.com to register or to learn more.
Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Emulation, Design Rule Checking, Clock Domain Crossing, VIP Transactors, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com
Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are the property of their respective owners.
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