Top 10 Aldec Design and Verification Blog Articles from 2013
Henderson, NV – January 6, 2014 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for SoC and ASIC designs, publishes a weekly Design and Verification Blog covering news, popular methodologies, and helpful tips and features authored by our top engineers. Below are the most viewed articles from 2013.
Productivity Boosting Features
HW/SW Emulation and Functional Verification of Xilinx FPGAs
Tools, Resources and Training for VHDL Users
DO-254: Insights from a DER
An Interview with FAA Consultant DER, Randall Fulton
Riviera-PRO Enables Class Hierarchy Visualization
For UVM-Based Verification Environments
Legacy Schematic Designs Giving you a Headache?
Retargeting Legacy Designs for New Technology
Verilog-AMS & Multi-Level Simulation
Aldec and Tanner EDA Bridge Digital and Analog Design Flows
HW Designers: Brush up on your SV with Online Training
Fast Track to SystemVerilog for Verilog Users
Following the Roadmap to Successful Traceability
Mission Possible for DO-254 Compliance
To Accelerate DSP Design Development
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com
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|Media Contact:||Aldec, Inc.
Christina Toole, Corporate Marketing Manager
+ (702) 990-4400