Aldec Releases Automated Static Linting and CDC Analysis for Microchip FPGA and SoC FPGA Designs February 06 Verifying at a Higher Level of Abstraction June 22 Riviera-PRO Supports OpenCPI for Heterogeneous Embedded Computing of Mission-Critical Applications June 01 Advancing VHDL’s Verification Capabilities with VHDL-2019 Protected Types March 29 Aldec Suspends all EDA Sales and Distribution Transactions in Russia March 14 View all news
VHDL/SystemVerilog RTL verification environment by cocotb Mar 29 (Webinar, Tokyo, Japan (Online)) Introduction to Logic Simulator Programming Interfaces for FPGA DesignsPart 1: The Power of Verilog’s PLI & VPI (US) Apr 13 (Webinar, Online) Introduction to Logic Simulator Programming Interfaces for FPGA DesignsPart 1: The Power of Verilog’s PLI & VPI (EU) Apr 13 (Webinar, Online) Introduction to Logic Simulator Programming Interfaces for FPGA DesignsPart 2: The Power of VHDL’s VHPI (US) Apr 27 (Webinar, Online) Introduction to Logic Simulator Programming Interfaces for FPGA DesignsPart 2: The Power of VHDL’s VHPI (EU) Apr 27 (Webinar, Online) View all events
Linting and CDC for Microchip FPGAs webinar (hosted by Microchip) Engineering best practices for Python-based testbenches with cocotb Optimizing Simulations for Efficient Coverage Collection Assertions-Based Verification for VHDL Designs CDC Verification with Hard IP Blocks View all webinars
