Cobham Gaisler successfully verifies its first RISC-V processor, NOEL-V, using Aldec’s Riviera-PRO for HDL Simulation January 28 Aldec Enhances Riviera-PRO’s VHDL and UVVM Support December 17 Aldec’s new FPGA-based NVMe Data Storage Solution Targets High Performance Computing Applications December 12 Aldec’s Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM December 03 Aldec’s Latest Embedded Development Platform is First to Feature Largest PolarFire and SmartFusion2 FPGAs on a Single Board November 26 View all news
Creating an AXI4 Lite, Transaction Based VHDL Testbench with OSVVM (EU) Feb 20 (Webinar, Online) Creating an AXI4 Lite, Transaction Based VHDL Testbench with OSVVM (US) Feb 20 (Webinar, Online) FPGA 2020 Feb 23 - 25 (Industry Event, Seaside, CA) Embedded World 2020 Feb 25 - 27 (Industry Event, Nuremberg, Germany) Shortening verification time of safety critical projects (EU) Feb 27 (Webinar, Online) View all events
Using ALINT-PRO to Verify Clock Domain Crossing Issues in FPGA designs How to Develop High-Performance Deep Learning Applications on FPGA-based Edge Devices Six Automated Steps to Design Partitioning for Multi-FPGA Prototyping Boards How to plan a DO-254 compliant verification process for FPGA designs VHDL testbenches using models, scoreboards and transactions View all webinars
