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A Proven EDA Solutions Provider makes all the difference.

Our promise to deliver leading verification methodologies that support the latest Ianguage standards allows our customers to grow while leveraging evolving technologies.

FPGA Design

FPGA Vendors Support Simulation and Debugging Project Management Graphical/Text Design Entry Documentation HTML/PDF

Hardware Prototyping

Scalable HES™ Prototyping Platform HES Proto-AXI Interconnect Multi-FPGA Design Partitioning ARM Cortex Support RTAX/RTSX Prototyping

Functional Verification

Metric Driven Verification UVM Transaction Debugging UVM, OVM and VMM OS-VVM™Static Linting CDC and RDC Verification QEMU Co-Sim

Requirements Management

Traceability Team-Based Methodology Requirements Capture Documentation and Reporting Tests Management Change Impact Analysis

Hardware Emulation Solutions

SoC Co-emulation UVM Simulation Acceleration Scalability of Acceleration Verification IP SoC Partitioning Emulation Debugging

High Performance Computing

Computer Vision Encryption & Security Genome Alignment High Frequency Trading Large Scale HPC Embedded HPC

DO-254 Compliance

HDL Coding Standards Tool Assessment and Qualification Process FPGA Level In-Target Testing HDL Detailed Design and Verification DO-254 Templates and Checklists

Specialized Applications

Regression Manager Encryption DSP and RF Co-Simulation

FPGA Embedded Solutions

Deep Learning Using Zynq US+ FPGA FPGA-based NVMe Data Storage Internet of Things (IoT)Automotive ADAS Networking Aldec 4K UltraHD Imaging Solutions Python and PYNQ COVID-19 Detection

Newsroom

Powerful FPGA Design Creation and Simulation IDE Adds VHDL-2019 Support & OSVVM Enhancements January 20 Riviera-PRO™: OSVVM 2020.08 inclusion, enhanced language support, and new debugging features aim to boost productivity December 08 SemiWiki: Aldec Adds Simulation Acceleration for Microchip FPGAs November 10 Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs November 03 Aldec’s TySOM Family of Embedded System Development Solutions Now Supports Xilinx PYNQ (Python Productivity for Zynq) October 21 View all news

Events

Fast Track to Riviera-PRO, Part 1: Design Entry and Simulation (US) Feb 25 (Webinar, Online) Fast Track to Riviera-PRO, Part 1: Design Entry and Simulation (EU) Feb 25 (Webinar, Online) Fast Track to Riviera-PRO, Part 2: Advanced Debugging, Code Coverage and Scripting (EU) Mar 18 (Webinar, Online) Fast Track to Riviera-PRO, Part 2: Advanced Debugging, Code Coverage and Scripting (US) Mar 18 (Webinar, Online) Achieve DO-254 Compliance with the Industry’s Most Comprehensive HDL Coding Guidelines (EU) Mar 25 (Webinar, Online) View all events

Recorded Webinars

Functional Verification of Clock Domain Crossing Issues Accelerating Verification Component development with OSVVM Model Independent Transactions Debugging Multi-Core Designs using Vitis + Aldec Riviera-PRO Co-Simulation for Zynq US+ MPSoC Accelerating Large Image and Signal Processing FPGA Design Developments with TySOM-3A-ZU19EG and PYNQ How to Build PCIe Speed Adapters for In-Circuit SoC Emulation View all webinars

Quicklinks

Product Updates Online Support Demonstration Videos Evaluations Search Resources Search Products University Programs Careers Blog Online Training Webinars White Papers

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