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Our promise to deliver leading verification methodologies that support the latest Ianguage standards allows our customers to grow while leveraging evolving technologies.

FPGA Design

FPGA Vendors Support Simulation and Debugging Project Management Graphical/Text Design Entry Documentation HTML/PDF

Hardware Prototyping

Scalable HES™ Prototyping Platform HES Proto-AXI Interconnect Multi-FPGA Design Partitioning ARM Cortex Support RTAX/RTSX Prototyping

Functional Verification

Metric Driven Verification UVM Transaction Debugging UVM, OVM and VMM OS-VVM™Static Linting CDC and RDC Verification QEMU Co-Sim

Requirements Management

Traceability Team-Based Methodology Requirements Capture Tests Management Documentation and Reporting Change Impact Analysis

Hardware Emulation Solutions

SoC Co-emulation UVM Simulation Acceleration Scalability of Acceleration Verification IP SoC Partitioning Emulation Debugging

High Performance Computing

Computer Vision Encryption & Security Genome Alignment High Frequency Trading Large Scale HPC Embedded HPC

DO-254 Compliance

HDL Coding Standards Tool Assessment and Qualification Process FPGA Level In-Target Testing HDL Detailed Design and Verification DO-254 Templates and Checklists

Specialized Applications

Regression Manager Encryption DSP and RF Co-Simulation

FPGA Embedded Solutions

Deep Learning Using Zynq US+ FPGA FPGA-based NVMe Data Storage Internet of Things (IoT)Automotive ADAS Networking Aldec 4K UltraHD Imaging Solutions Python and PYNQ COVID-19 Detection

Newsroom

Airborne System Design Assurance: Aldec Adds 60+ New HDL Rules to ALINT-PRO’s DO-254 Plug-In March 04 Powerful FPGA Design Creation and Simulation IDE Adds VHDL-2019 Support & OSVVM Enhancements January 20 Riviera-PRO™: OSVVM 2020.08 inclusion, enhanced language support, and new debugging features aim to boost productivity December 08 SemiWiki: Aldec Adds Simulation Acceleration for Microchip FPGAs November 10 Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs November 03 View all news

Events

VHDL-2019: Just the New Stuff Part 1: Interfaces, Conditional Analysis, File IO, and The New Environment (US) Apr 22 (Webinar, Online) VHDL-2019: Just the New Stuff Part 1: Interfaces, Conditional Analysis, File IO, and The New Environment (EU) Apr 22 (Webinar, Online) VHDL-2019: Just the New Stuff Part 2: Protected Types and Verification Data Structures (EU) May 06 (Webinar, Online) VHDL-2019: Just the New Stuff Part 2: Protected Types and Verification Data Structures (US) May 06 (Webinar, Online) VHDL-2019: Just the New Stuff Part 3: RTL Enhancements (US) May 27 (Webinar, Online) View all events

Recorded Webinars

The impact of AMC-152A guidance on design and verification process of DO-254 projects Achieve DO-254 Compliance with the Industry’s Most Comprehensive HDL Coding Guidelines Fast Track to Riviera-PRO, Part 2: Advanced Debugging, Code Coverage and Scripting Fast Track to Riviera-PRO, Part 1: Design Entry and Simulation Functional Verification of Clock Domain Crossing Issues View all webinars

Quicklinks

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