Hardware Lifecycle Data Management for Teams April 01 Latest TySOM Kit Accelerates the Development of AI, DNN and Other Algorithm Acceleration-dependent Applications Plus Aids SoC Prototyping February 26 Aldec facilitates design prototyping in FPGA and prototype testing with new HES Proto-AXI January 22 Aldec shortens time of ASIC design prototype bring-up in FPGA with HES-DVM Proto mode January 14 VHDL 2018 Support & Enhanced Automation - Aldec adds VHDL Standard 1076-2018 extensions and automatic coverage model generation to Riviera-PRO™ November 13 View all news
VHDL testbenches using models, scoreboards and transactions (EU) Apr 25 (Webinar, Online) VHDL testbenches using models, scoreboards and transactions (US) Apr 25 (Webinar, Online) Design Automation Conference (DAC) 2019 Jun 02 - 06 (Industry Event, Las Vegas, NV) View all events
SoC Emulation in FPGA with ARM Hardware Model Managing DO-254 Compliant Documents Verifying Finite State Machines with Aldec Products From Traceability to Reusability for Safety-Critical FPGA Projects Partitioning Design for Custom or In-house Designed Multi-FPGA Board View all webinars
