Aldec’s Focus for Arm TechCon is on Deep Neural Network and Machine Learning Application Development October 02 Aldec cuts ASIC design prototype bring-up time with HES-DVM’s automatic partitioning tool and faster HDL-to-FPGA compilation times September 24 SoC & ASIC designers to benefit greatly from multiple HES Proto-AXI™ enhancements September 09 Riviera-PRO™ users to benefit from automatic UVM register generation plus the latest verification methodology libraries June 18 Introducing SyntHESer, Aldec’s proprietary high-speed synthesizer for HES emulation and prototyping June 03 View all news
DVCon 2019 Oct 29 - 30 (Industry Event, Munich, Germany) Supercomputing 2019 Nov 18 - 21 (Industry Event, Denver, CO) View all events
Six Automated Steps to Design Partitioning for Multi-FPGA Prototyping Boards How to plan a DO-254 compliant verification process for FPGA designs VHDL testbenches using models, scoreboards and transactions SoC Emulation in FPGA with ARM Hardware Model Managing DO-254 Compliant Documents View all webinars
