SemiWiki: HW and SW Co-verification for Xilinx Zynq SoC FPGAs July 03 Aldec and Silvaco present Mixed-Signal Simulation Solution at DAC 2017 June 15 Aldec @ DAC 2017: Presenting Breakthrough Innovations in SoC Design & Verification June 06 EE Web: The Benefits of HW/SW Co-Simulation for Zynq-Based Designs June 06 Intelligent Areospace: In safe hands: requirement-based testing for design assurance of complex, safety-critical components with high impacts of failure May 30 View all news
Microsemi Space Forum India Jul 25 (Industry Event, Online) SystemVerilog Assertion Workshop Jul 26 (Training, Tokyo, Japan) Microsemi Space Forum India Jul 27 (Industry Event, Online) Riviera-PRO Advanced Verification Workshop Jul 28 (Training, Tokyo, Japan) Design Rule Check and CDC Verification Workshop Aug 02 (Training, Tokyo, Japan) View all events
Addressing the Challenges of SoC Verification in practice using Co-Simulation FPGA Accelerator for Genome Aligner - ReneGENE From OSVVM VHDL Functional Coverage to UCIS-based Database UVVM - A game changer for FPGA VHDL Verification Advanced RTL Debugging for Zynq SoC Designs View all webinars
