What’s involved in simulation of a complex SoC FPGA like Versal ACAP? February 08 Aldec @ DAC 2023: Presenting Design Verification Tools and Solutions for FPGAs and SoCs June 26 Riviera-PRO Supports System Simulation of AMD® Versal™ ACAP Designs June 14 The avionics industry’s growing need for TLM May 18 Aldec and Thales to Co-Present at Certification Together International Conference 2023 May 01 View all news
Static and Dynamic CDC Verification of AXI4 Stream-based IPs (US) Oct 17 (Webinar, Online) Static and Dynamic CDC Verification of AXI4 Stream-based IPs (EU) Oct 17 (Webinar, Online) Verify Clock Domain Crossing Issues in FPGA Designs Using ALINT-PRO Oct 23 (Webinar, Tokyo, Japan ) Design Solution Forum 2024 Oct 25 (Industry Event, Kawasaki, Japan ) It's never too late to assertion verification Oct 30 (Webinar, Tokyo, Japan ) View all events
The Development and Evolution of Verilog & SystemVerilog Using OSVVM’s AXI4 Verification Components (Part 2) Writing Tests and Configuring the AXI4 VCs Using OSVVM’s AXI4 Verification Components (Part 1) Creating the AXI4 Testbench / Test Harness Why Should Our Team be Using VHDL + OSVVM for Verification? Making a Structured VHDL Testbench – A Demo for Beginners View all webinars