Aldec’s HES UltraScale+ Reconfigurable Accelerator and Northwest Logic’s PCI Express Cores Provide Proven PCI Express Solution April 11 Aldec to showcase Verification Spectrum for SoC FPGAs at Embedded World 2018 February 21 QuickLogic Announces Partnership with Aldec for eFPGA Simulation Flow February 20 Aldec presents ‘Dealing with CDC verification complexity in large-scale FPGA designs’ at FPGA Forum 2018 February 08 Reconfigurable high-performance routers and switches - made easy February 07 View all news
QEMU Co-emulation with FPGA (EU) Apr 19 (Webinar, Online) QEMU Co-emulation with FPGA (US) Apr 19 (Webinar, Online) Spec-TRACER Workshop Apr 20 (Training, Tokyo, Japan) VHDL (Basic+Simulation) Training Apr 24 - 25 (Training, Tokyo, Japan) Universal VHDL Verification Methodology (UVVM) – The standardized open source VHDL testbench architecture (EU) Apr 26 (Webinar, Online) View all events
Taming Testbench Messaging and Error Reporting with OSVVM's Logs and Alerts Designing FPGA-based ADAS Application - Driver Drowsiness Detection Verifying Resets and Reset Domain Crossings Extending IBM Rational DOORS Traceability for FPGA Designs Verification Methodology for Large-Scale FPGA designs View all webinars
