Aldec shortens time of ASIC design prototype bring-up in FPGA with HES-DVM Proto mode January 14 VHDL 2018 Support & Enhanced Automation - Aldec adds VHDL Standard 1076-2018 extensions and automatic coverage model generation to Riviera-PRO™ November 13 Aldec’s “Hardware and Software Co-verification in Hybrid Simulation and Emulation Environment with QEMU” DVCon Europe tutorial to demonstrate how engineers can obtain a holistic view over their SoC design October 22 A View from Above October 15 Visible Benefits October 15 View all news
Managing DO-254 Compliant Documents Verifying Finite State Machines with Aldec Products From Traceability to Reusability for Safety-Critical FPGA Projects Partitioning Design for Custom or In-house Designed Multi-FPGA Board Tool Qualification – DO-254, DO-330, and ISO 26262 Approaches View all webinars
