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Our promise to deliver leading verification methodologies that support the latest Ianguage standards allows our customers to grow while leveraging evolving technologies.

FPGA Design

FPGA Vendors Support Simulation and Debugging Project Management Graphical/Text Design Entry Documentation HTML/PDF

Hardware Prototyping

Scalable HES™ Prototyping Platform HES Proto-AXI Interconnect Multi-FPGA Design Partitioning ARM Cortex Support RTAX/RTSX Prototyping

Functional Verification

Metric Driven Verification UVM Transaction Debugging UVM, OVM and VMM OS-VVM™Static Linting CDC and RDC Verification Co-Simulation with QEMU and Riviera-PRO

FPGA Embedded Solutions

Deep Learning Using Zynq US+ FPGA FPGA-based NVMe Data Storage Internet of Things (IoT)Automotive ADAS Networking Aldec 4K UltraHD Imaging Solutions Python and PYNQ COVID-19 Detection

Hardware Emulation Solutions

SoC Co-emulation UVM Simulation Acceleration Scalability of Acceleration Verification IP SoC Partitioning Emulation Debugging

High Performance Computing

Computer Vision Encryption & Security Genome Alignment High Frequency Trading Large Scale HPC Embedded HPC

DO-254 Compliance

HDL Coding Standards Tool Assessment and Qualification Process FPGA Level In-Target Testing HDL Detailed Design and Verification DO-254 Templates and Checklists

Specialized Applications

Regression Manager Encryption DSP and RF Co-Simulation

Newsroom

Advancing VHDL’s Verification Capabilities with VHDL-2019 Protected Types March 29 Aldec Suspends all EDA Sales and Distribution Transactions in Russia March 14 Industry’s First use of TLM for the At-Speed Verification of a PCIe-Based Avionics Design Requiring DO-254 Compliance January 13 Productivity Through Methodology: Aldec Adds UVM Generator to Riviera-PRO™ Plus Updates Its OSVVM and UVVM Libraries November 16 New HES Board is Ideal for Prototyping and Emulating Medium to Large ASIC & SoC Designs July 19 View all news

Events

Better FPGA Verification with VHDL

Part 1: OSVVM - Leading Edge Verification for the VHDL Community (US) May 26 (Webinar, Online) Better FPGA Verification with VHDL

Part 1: OSVVM - Leading Edge Verification for the VHDL Community (EU) May 26 (Webinar, Online) Better FPGA Verification with VHDL

Part 2: Faster than "Lite" Verification Component Development with OSVVM (US) Jun 09 (Webinar, Online) Better FPGA Verification with VHDL

Part 2: Faster than "Lite" Verification Component Development with OSVVM (EU) Jun 09 (Webinar, Online) Better FPGA Verification with VHDL

Part 3: OSVVM's Test Reports and Simulator Independent Scripting (US) Jun 16 (Webinar, Online) View all events

Recorded Webinars

FPGA Design/Verification Best-Practices for Quality and Efficiency

Part 4: Code, Functional and Specification Coverage FPGA Design/Verification Best-Practices for Quality and Efficiency

Part 3: Randomization – The Why, When, What & How FPGA Design/Verification Best-Practices for Quality and Efficiency Part 2: FPGA Verification Architecture Optimization with UVVM FPGA Design/Verification Best-Practices for Quality and Efficiency Part 1: FPGA Design Architecture Optimization Running CDC Analysis with Xilinx Parameterized Macros View all webinars

Quicklinks

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