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A Proven EDA Solutions Provider makes all the difference.

Our promise to deliver leading verification methodologies that support the latest Ianguage standards allows our customers to grow while leveraging evolving technologies.

FPGA Design

FPGA Vendors Support Simulation and Debugging Project Management Graphical/Text Design Entry Documentation HTML/PDF

Prototyping

Scalable HES™ Prototyping Platform HES Proto-AXI Host Interface Multi-FPGA Design Partitioning ARM Cortex Support RTAX/RTSX Prototyping

Functional Verification

Assertions/Functional Coverage UVM Transaction Debugging UVM, OVM and VMM OS-VVM™Code Coverage Static Linting CDC Verification

Requirements Management

Traceability Team-Based Methodology Change Impact Analysis Tests Management Requirements Capture Documentation and Reporting

Hardware Emulation Solutions

Co-emulation UVM Simulation Acceleration Scalability of Acceleration Verification IP SoC Partitioning Emulation Debugging

High Performance Computing

Large Scale HPC Embedded HPC

DO-254 Compliance

HDL Coding Standards Tool Assessment and Qualification Process FPGA Level In-Target Testing HDL Detailed Design and Verification DO-254 Templates and Checklists

Specialized Applications

Regression Manager Encryption DSP and RF Co-Simulation

Embedded Solutions

Internet of Things (IoT)Automotive ADAS

Newsroom

Aldec @ DVCon India 2017 - accelerating SoC validation by extending QEMU open-source capabilities September 12 Aldec solves ASIC design partitioning challenges with HES-DVM Proto mode September 11 Intelligent Areospace: Reprogrammable prototyping solutions: a must for space design verification September 01 Embedded Vision: Look and Identify August 30 Benefit from the power of the latest SystemVerilog subset constructs – with confidence August 08 View all news

Events

Design Rule Check and CDC Verification Workshop Sep 22 (Training, Tokyo, Japan) Riviera-PRO Advanced Verification Workshop Sep 27 (Training, Tokyo, Japan) How to connect an FPGA board to AWS cloud for high-performance Industrial IoT edge processing (EU) Sep 28 (Webinar, Online) How to connect an FPGA board to AWS cloud for high-performance Industrial IoT edge processing (US) Sep 28 (Webinar, Online) Transaction Level Co-Emulation Workshop Sep 29 (Training, Tokyo, Japan) View all events

Recorded Webinars

Aiding ASIC Design Partitioning for multi-FPGA Prototyping Fast Track to Riviera-PRO, Part 2: Advanced Debugging, Code Coverage and Scripting Benefits of Requirements Management for Safety-Critical FPGA Projects Fast Track to Riviera-PRO, Part 1: Design Entry and Simulation Addressing the Challenges of SoC Verification in practice using Co-Simulation View all webinars

Quicklinks

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