Benefit from the power of the latest SystemVerilog subset constructs – with confidence August 08 SemiWiki: HW and SW Co-verification for Xilinx Zynq SoC FPGAs July 03 Aldec and Silvaco present Mixed-Signal Simulation Solution at DAC 2017 June 15 Aldec @ DAC 2017: Presenting Breakthrough Innovations in SoC Design & Verification June 06 EE Web: The Benefits of HW/SW Co-Simulation for Zynq-Based Designs June 06 View all news
VHDL (Basic+Simulation) Training Aug 22 - 23 (Training, Tokyo, Japan) Benefits of Requirements Management for Safety-Critical FPGA Projects (EU) Aug 24 (Webinar, Online) Benefits of Requirements Management for Safety-Critical FPGA Projects (US) Aug 24 (Webinar, Online) Transaction Level Co-Emulation Workshop Aug 25 (Training, Tokyo, Japan) Spec-TRACER Workshop Aug 30 (Training, Tokyo, Japan) View all events
Addressing the Challenges of SoC Verification in practice using Co-Simulation FPGA Accelerator for Genome Aligner - ReneGENE From OSVVM VHDL Functional Coverage to UCIS-based Database UVVM - A game changer for FPGA VHDL Verification Advanced RTL Debugging for Zynq SoC Designs View all webinars
