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Aldec and Codasip at Embedded World: Showcasing an Integrated UVM Simulation Environment for Verifying Custom Instructions with RISC-V Cores February 19 Cobham Gaisler successfully verifies its first RISC-V processor, NOEL-V, using Aldec’s Riviera-PRO for HDL Simulation January 28 Aldec Enhances Riviera-PRO’s VHDL and UVVM Support December 17 Aldec’s new FPGA-based NVMe Data Storage Solution Targets High Performance Computing Applications December 12 Aldec’s Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM December 03 View all news
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