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Our promise to deliver leading verification methodologies that support the latest Ianguage standards allows our customers to grow while leveraging evolving technologies.

Powerful FPGA Design Creation and Simulation IDE Adds VHDL-2019 Support & OSVVM Enhancements January 20 Riviera-PRO™: OSVVM 2020.08 inclusion, enhanced language support, and new debugging features aim to boost productivity December 08 SemiWiki: Aldec Adds Simulation Acceleration for Microchip FPGAs November 10 Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs November 03 Aldec’s TySOM Family of Embedded System Development Solutions Now Supports Xilinx PYNQ (Python Productivity for Zynq) October 21 View all news
Fast Track to Riviera-PRO, Part 1: Design Entry and Simulation (US) Feb 25 (Webinar, Online) Fast Track to Riviera-PRO, Part 1: Design Entry and Simulation (EU) Feb 25 (Webinar, Online) Fast Track to Riviera-PRO, Part 2: Advanced Debugging, Code Coverage and Scripting (EU) Mar 18 (Webinar, Online) Fast Track to Riviera-PRO, Part 2: Advanced Debugging, Code Coverage and Scripting (US) Mar 18 (Webinar, Online) Achieve DO-254 Compliance with the Industry’s Most Comprehensive HDL Coding Guidelines (EU) Mar 25 (Webinar, Online) View all events
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