Riviera-PRO™ users to benefit from automatic UVM register generation plus the latest verification methodology libraries June 18 Introducing SyntHESer, Aldec’s proprietary high-speed synthesizer for HES emulation and prototyping June 03 Aldec @ DAC 2019: Celebrating its 35th Anniversary and focusing on design acceleration, co-verification and mixed-signal May 15 Hardware Lifecycle Data Management for Teams April 01 Latest TySOM Kit Accelerates the Development of AI, DNN and Other Algorithm Acceleration-dependent Applications Plus Aids SoC Prototyping February 26 View all news
VHDL testbenches using models, scoreboards and transactions SoC Emulation in FPGA with ARM Hardware Model Managing DO-254 Compliant Documents Verifying Finite State Machines with Aldec Products From Traceability to Reusability for Safety-Critical FPGA Projects View all webinars
