日本語 Sign In | Register

A Proven EDA Solutions Provider makes all the difference.

Our promise to deliver leading verification methodologies that support the latest Ianguage standards allows our customers to grow while leveraging evolving technologies.

FPGA Design

FPGA Vendors Support Simulation and Debugging Project Management Graphical/Text Design Entry Documentation HTML/PDF

Hardware Prototyping

Scalable HES™ Prototyping Platform HES Proto-AXI Interconnect Multi-FPGA Design Partitioning ARM Cortex Support RTAX/RTSX Prototyping

Functional Verification

Metric Driven Verification UVM Transaction Debugging UVM, OVM and VMM OS-VVM™Static Linting CDC and RDC Verification QEMU Co-Sim

Requirements Management

Traceability Team-Based Methodology Documentation and Reporting Tests Management Requirements Capture Change Impact Analysis

Hardware Emulation Solutions

SoC Co-emulation UVM Simulation Acceleration Scalability of Acceleration Verification IP SoC Partitioning Emulation Debugging

High Performance Computing

Computer Vision Encryption & Security Genome Alignment High Frequency Trading Large Scale HPC Embedded HPC

DO-254 Compliance

HDL Coding Standards Tool Assessment and Qualification Process FPGA Level In-Target Testing HDL Detailed Design and Verification DO-254 Templates and Checklists

Specialized Applications

Regression Manager Encryption DSP and RF Co-Simulation

FPGA Embedded Solutions

Deep Learning Using Zynq US+ FPGA FPGA-based NVMe Data Storage Internet of Things (IoT)Automotive ADAS Networking Aldec 4K UltraHD Imaging Solutions

Newsroom

Aldec’s TySOM Embedded Development Kits are Now Qualified for AWS IoT Greengrass August 05 Aldec Provides Static Verification for RISC-V Designs with the latest release of ALINT-PRO July 22 Aldec @ DAC 2020: Presenting RISC-V Verification Methodologies and Solutions July 15 Aldec Adds Customizable Tool Qualification Data Package to ALINT-PRO™ for DO-254 Projects June 30 New to Riviera-PRO™: VHDL-2019 Support and a Versatile UVM Registers Window June 24 View all news

Events

RISC-V Design & Verification with FPGA Hardware In The Loop (EU) Sep 24 (Webinar, Online) RISC-V Design & Verification with FPGA Hardware In The Loop (US) Sep 24 (Webinar, Online) Static Verification for RISC-V Cores and SoCs (US) Oct 01 (Webinar, Online) Static Verification for RISC-V Cores and SoCs (EU) Oct 01 (Webinar, Online) DVCon EU 2020 Oct 27 - 28 (Industry Event, Online) View all events

Recorded Webinars

UVM-based Verification of Custom Instructions with RISC-V Cores UVM Simulation-based environment for Ibex RISC-V CPU core with Google RISC-V DV How to enforce HDL coding standards and gain the overall design review to meet DO-254 objectives Creating Better Self-Checking FPGA Verification Tests with Open Source VHDL Verification Methodology (OSVVM) Use Python and bring joy back to verification View all webinars

Quicklinks

Product Updates Online Support Demonstration Videos Evaluations Search Resources Search Products University Programs Careers Blog Online Training Webinars White Papers

Ask Us a Question

Incorrect data entered.

Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.

Internal error occurred. Your question was not submitted. Please contact us using Feedback form.

We use cookies to ensure we give you the best user experience and to provide you with content we believe will be of relevance to you. If you continue to use our site, you consent to our use of cookies. A detailed overview on the use of cookies and other website information is located in our Privacy Policy.