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A Proven EDA Solutions Provider makes all the difference.

Our promise to deliver leading verification methodologies that support the latest Ianguage standards allows our customers to grow while leveraging evolving technologies.

FPGA Design

FPGA Vendors Support Simulation and Debugging Project Management Graphical/Text Design Entry Documentation HTML/PDF

Hardware Prototyping

Scalable HES™ Prototyping Platform HES Proto-AXI Interconnect Multi-FPGA Design Partitioning ARM Cortex Support RTAX/RTSX Prototyping

Functional Verification

Metric Driven Verification Universal Verification Methodology (UVM)Open Source VHDL Verification Methodology (OSVVM)Universal VHDL Verification Methodology (UVVM)Cocotb Static Linting Co-Simulation with QEMU and Riviera-PRO CDC and RDC Verification

FPGA Embedded Solutions

Deep Learning Using Zynq US+ FPGA FPGA-based NVMe Data Storage Internet of Things (IoT)Automotive ADAS Networking Aldec 4K UltraHD Imaging Solutions Python and PYNQ COVID-19 Detection

Hardware Emulation Solutions

SoC Co-emulation UVM Simulation Acceleration Scalability of Acceleration Verification IP SoC Partitioning Emulation Debugging

High Performance Computing

Computer Vision Encryption & Security Genome Alignment High Frequency Trading Large Scale HPC Embedded HPC

DO-254 Compliance

Traceability HDL Coding Standards Tool Assessment and Qualification Process FPGA Level In-Target Testing HDL Detailed Design and Verification DO-254 Templates and Checklists

Specialized Applications

Regression Manager Encryption DSP and RF Co-Simulation

Newsroom

What’s involved in simulation of a complex SoC FPGA like Versal ACAP? February 08 Aldec @ DAC 2023: Presenting Design Verification Tools and Solutions for FPGAs and SoCs June 26 Riviera-PRO Supports System Simulation of AMD® Versal™ ACAP Designs June 14 The avionics industry’s growing need for TLM May 18 Aldec and Thales to Co-Present at Certification Together International Conference 2023 May 01 View all news

Events

The Development and Evolution of Verilog & SystemVerilog (EU) Oct 10 (Webinar, Online) The Development and Evolution of Verilog & SystemVerilog (US) Oct 10 (Webinar, Online) Static and Dynamic CDC Verification of AXI4 Stream-based IPs (US) Oct 17 (Webinar, Online) Static and Dynamic CDC Verification of AXI4 Stream-based IPs (EU) Oct 17 (Webinar, Online) Verify Clock Domain Crossing Issues in FPGA Designs Using ALINT-PRO Oct 23 (Webinar, Tokyo, Japan ) View all events

Recorded Webinars

Using OSVVM’s AXI4 Verification Components (Part 2) Writing Tests and Configuring the AXI4 VCs Using OSVVM’s AXI4 Verification Components (Part 1) Creating the AXI4 Testbench / Test Harness Why Should Our Team be Using VHDL + OSVVM for Verification? Making a Structured VHDL Testbench – A Demo for Beginners Turbocharge your FPGA Simulation Workflows Part 3: High-Performance RTL Simulation Workflow with Libero and Active-HDL View all webinars

Quicklinks

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