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A Proven EDA Solutions Provider makes all the difference.

Our promise to deliver leading verification methodologies that support the latest Ianguage standards allows our customers to grow while leveraging evolving technologies.

FPGA Design

FPGA Vendors Support Simulation and Debugging Project Management Graphical/Text Design Entry Documentation HTML/PDF

Hardware Prototyping

Scalable HES™ Prototyping Platform HES Proto-AXI Interconnect Multi-FPGA Design Partitioning ARM Cortex Support RTAX/RTSX Prototyping

Functional Verification

Metric Driven Verification UVM Transaction Debugging UVM, OVM and VMM OS-VVM™Static Linting CDC and RDC Verification QEMU Co-Sim

Requirements Management

Traceability Team-Based Methodology Tests Management Requirements Capture Documentation and Reporting Change Impact Analysis

Hardware Emulation Solutions

SoC Co-emulation UVM Simulation Acceleration Scalability of Acceleration Verification IP SoC Partitioning Emulation Debugging

High Performance Computing

Computer Vision Encryption & Security Genome Alignment High Frequency Trading Large Scale HPC Embedded HPC

DO-254 Compliance

HDL Coding Standards Tool Assessment and Qualification Process FPGA Level In-Target Testing HDL Detailed Design and Verification DO-254 Templates and Checklists

Specialized Applications

Regression Manager Encryption DSP and RF Co-Simulation

FPGA Embedded Solutions

Deep Learning Using Zynq US+ FPGA FPGA-based NVMe Data Storage Internet of Things (IoT)Automotive ADAS Networking Aldec 4K UltraHD Imaging Solutions

Newsroom

InterMotion Technology boosts IP verification productivity for Lattice Semiconductor’s CrossLink FPGA family using Aldec’s Active-HDL March 24 Aldec to Present at Certification Together International Conference March 02 Aldec and Codasip at Embedded World: Showcasing an Integrated UVM Simulation Environment for Verifying Custom Instructions with RISC-V Cores February 19 Cobham Gaisler successfully verifies its first RISC-V processor, NOEL-V, using Aldec’s Riviera-PRO for HDL Simulation January 28 Aldec Enhances Riviera-PRO’s VHDL and UVVM Support December 17 View all news

Events

UVVM steps up a gear: A review of some of the new features in this standardized VHDL verification methodology (EU) Apr 02 (Webinar, Online) UVVM steps up a gear: A review of some of the new features in this standardized VHDL verification methodology (US) Apr 02 (Webinar, Online) CAIF 2020 Apr 16 - 17 (Industry Event, Shanghai, China) 3-Day DO-254 Practitioner’s Course May 13 - 15 (Training, Las Vegas, NV) View all events

Recorded Webinars

Six Automated Steps to Design Partitioning for Multi-FPGA Prototyping Boards Hierarchical CDC verification with ALINT-PRO Shortening the verification time of safety critical projects Creating an AXI4 Lite, Transaction Based VHDL Testbench with OSVVM Using ALINT-PRO to Verify Clock Domain Crossing Issues in FPGA designs View all webinars

Quicklinks

Product Updates Online Support Demonstration Videos Evaluations Search Resources Search Products University Programs Careers Blog Online Training Webinars White Papers

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