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Riviera-PRO Supports OpenCPI for Heterogeneous Embedded Computing of Mission-Critical Applications June 01 Advancing VHDL’s Verification Capabilities with VHDL-2019 Protected Types March 29 Aldec Suspends all EDA Sales and Distribution Transactions in Russia March 14 Industry’s First use of TLM for the At-Speed Verification of a PCIe-Based Avionics Design Requiring DO-254 Compliance January 13 Productivity Through Methodology: Aldec Adds UVM Generator to Riviera-PRO™ Plus Updates Its OSVVM and UVVM Libraries November 16 View all news
Better FPGA Verification with VHDL

Part 4: Advances in OSVVM's Verification Data Structures
Better FPGA Verification with VHDL

Part 3: OSVVM's Test Reports and Simulator Independent Scripting
Better FPGA Verification with VHDL

Part 2: Faster than Lite Verification Component Development with OSVVM
Better FPGA Verification with VHDL

Part 1: OSVVM: Leading Edge Verification for the VHDL Community
FPGA Design/Verification Best-Practices for Quality and Efficiency

Part 4: Code, Functional and Specification Coverage
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