Intelligent Aerospace: FPGA verification techniques for avionics applications September 05 SemiWiki: Optimization and verification wins in IoT designs August 17 Aldec Delivers Verification Support for Embedded Applications with New Xilinx Zynq-based TySOM Embedded Development Kit August 16 Embedded Computing Design: Verification is crucial for programmable SoC designs August 15 Aldec Increases Verification Productivity with the latest release of Riviera-PRO July 12 View all news
VHDL (Basic+Simulation) Training Sep 27 - 28 (Training, Tokyo, Japan) Riviera-PRO Advanced Verification Workshop Sep 29 (Training, Tokyo, Japan) Transaction Level Co-Emulation Workshop Sep 30 (Training, Tokyo, Japan) PSL Assertion Workshop Oct 05 (Training, Tokyo, Japan) SystemVerilog Assertion Workshop Oct 07 (Training, Tokyo, Japan) View all events
Advanced RTL Debugging for Zynq SoC Designs Efficient CDC Debugging Using Phase-based Methodology for Large FPGA/ASIC Multi-clock Designs Introduction to Aldec Riviera-PRO - High Performance Mixed-language Simulator Fast Track to ALINT-PRO: Design Entry and Linting DO-254: How to Formulate an Efficient PHAC View all webinars
