Aldec @ DAC 2023: Presenting Design Verification Tools and Solutions for FPGAs and SoCs June 26 Riviera-PRO Supports System Simulation of AMD® Versal™ ACAP Designs June 14 The avionics industry’s growing need for TLM May 18 Aldec and Thales to Co-Present at Certification Together International Conference 2023 May 01 Aldec Releases Automated Static Linting and CDC Analysis for Microchip FPGA and SoC FPGA Designs February 06 View all news
VHDL/SystemVerilog RTL verification environment by cocotb Dec 13 (Webinar, Tokyo, Japan ) Efficient CDC Debugging Using Phase-based Methodology Dec 20 (Webinar, Tokyo, Japan ) View all events
System Simulation of Versal ACAP Designs Ways to run cocotb: Makefiles, cocotb-test, or your custom setup FPGA Design Verification in a Nutshell (Part 3) Advanced Verification Methods FPGA Design Verification in a Nutshell (Part 2) Advanced Testbench Implementation FPGA Design Verification in a Nutshell (Part 1) Verification Planning View all webinars