Aldec’s Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM December 03 Aldec’s Latest Embedded Development Platform is First to Feature Largest PolarFire and SmartFusion2 FPGAs on a Single Board November 26 Developing Robust Finite State Machines Code With Lint Tools November 26 Aldec at SC19: Showcasing Multi-FPGA Partitioning Software for Multi-FPGA-based Algorithm Accelerators November 18 Aldec Provides the Industry’s Most-Comprehensive Portfolio of FMC Daughter Cards November 14 View all news
RISC-V Summit 2019 Dec 10 - 12 (Industry Event, San Jose, CA) Using ALINT-PRO to Verify Clock Domain Crossing Issues in FPGA designs (EU) Dec 12 (Webinar, Online) Using ALINT-PRO to Verify Clock Domain Crossing Issues in FPGA designs (US) Dec 12 (Webinar, Online) View all events
How to Develop High-Performance Deep Learning Applications on FPGA-based Edge Devices Six Automated Steps to Design Partitioning for Multi-FPGA Prototyping Boards How to plan a DO-254 compliant verification process for FPGA designs VHDL testbenches using models, scoreboards and transactions SoC Emulation in FPGA with ARM Hardware Model View all webinars
