Aldec Enables Class Hierarchy Visualization for UVM-Based Verification Environments
Henderson, NV – July 10, 2013 – Aldec, Inc., today announced the latest release of its mixed-language advanced verification platform, Riviera-PRO™ 2013.06. This release includes numerous enhancements, including class hierarchy visualization for UVM-based verification environments, enabling increased verification productivity.
“With enhanced UVM support, Riviera-PRO 2013.06 makes it easier for verification teams to deploy class-based Testbench environments”, said Dmitry Melnik, Product Manager, Aldec Software Division. “The new 'Classes' window available with this release provides essential information about the operation of verification environments that are based on the object-oriented library and dynamic data types.”
As the structure of UVM is defined by the hierarchy of SystemVerilog classes, it is essential that a verification platform provides proper insight into the object-oriented environments, while remaining consistent with standard source code and waveform viewing tools widely used by RTL design and verification engineers. Riviera-PRO 2013.06 presents SystemVerilog classes in the form of a hierarchical tree view, integrated with the rest of the IDE for easy cross-probing and navigation, and providing indication of class inheritance, methods, properties, and other important attributes.
The need for additional simulation performance is a key requirement in any verification process. With version 2013.06, Riviera-PRO celebrates another important milestone of simulation runtime improvement, demonstrating stunning 2—3x average speedup in simulations with code coverage enabled.
Also equipped with a new high-performance SystemVerilog random constraint solver, new UVM-aware debugging tools, and improved simulation capacity, Riviera-PRO 2013.06 increases verification performance, accelerates coverage closure, and provides design verification teams with the tool they need to achieve the productivity required by today’s economy and competition.
Complete list of new features and enhancements:
“What’s New” presentation:
Riviera-PRO 2013.06 is available today. Download the latest release from www.aldec.com/downloads. Current customers with valid maintenance receive the release at no additional cost.
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com
Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
|Media Contact:||Christina Toole, Aldec, Inc.