HES-DVM

 

HES-DVM Hybrid Verification Platform

HES-DVM™ is a fully automated and scalable hybrid verification environment for SoC and ASIC designs. Utilizing the latest co-emulation standards like SCE-MI or TLM and newest FPGA technology, hardware and software design teams obtain early access to the hardware prototype of the design. Working concurrently with one another they develop and verify high-level code with RTL accuracy and speed-effective SoC emulation or prototyping models reducing test time and a risk of silicon re-spins.

HES-DVM™ provides verification teams with multiple use modes including both emulation and physical prototyping techniques enabling SoC teams to work on a single platform.

 

 

Emulation Modes

Emulation modes include simulation acceleration, transaction level co-emulation and in-circuit emulation for chip and system level verification of SoC and ASIC designs. These use models enable many applications such as hardware and software co-verification utilizing TLM wrappers and high-speed AXI or AHB bus transactors to connect design residing in hardware with Virtual Platforms. Also included are powerful debugging tools that allow for 100% visibility into modules running in the FPGA, making the HES-DVM emulation platform as easy to use as an RTL simulator.

 

Key Features

Supported FPGA Boards

  • Aldec HES prototyping boards
  • Third party or in-house made custom boards 

 

Verification Interfaces

 

Automated Design Setup

  • Design compilation for SystemVerilog, Verilog and VHDL
  • Behavioral transactors compiler supporting SV DPI-C and SCE-MI SV-Connect
  • Incremental design synthesis with third party synthesis tools
  • Automatic partitioning and inter-FPGA connections
  • Automatic gated clock conversion with unlimited number of clock domains
  • Memory flow to map design memories to board or FPGA resources
  • Automatic code instrumentation for debugging
  • Self-constrained and automated FPGA implementation using vendor tools (Xilinx Vivado)
  • Server farms support LSF and SGE
  • User interfaces: GUI & TCL scripting

 

Debugging Capabilities

  • HVD technology for 100% visibility with reduced number of captured probes
  • Configurable triggering
  • Hardware breakpoints
  • Clocks control (Stop, Run, Step)
  • Saving debug data in waveform files: ASDB for Riviera-PRO and  FSDB for Verdi
  • Memory back-door access for read & write
  • HW Debugger tool with GUI to manage debug process
  • C/C++ HES Debug API

 

Physical Prototyping

Physical prototyping enables the highest clock rates, often close to the target ones, so it is ideal for verification in the real environment with devices sending and receiving real data streams. The HES-DVM aids in design partitioning, clock conversion and mapping to FPGA and facilitates designing inter-chip connections that utilize serialization techniques to overcome limitation of FPGA I/O.

 

Key Features

Supported FPGA Boards

  • Aldec HES prototyping boards
  • Third party or in-house made custom boards 

 

Automated Design Setup

  • Fast-track setup for multi-FPGA prototyping
  • Guided partitioning using design structure model and top-down strategy
  • Instance logic replication in many partitions for clocking modules
  • Monitoring utilized logic resources and interconnections
  • Dry run and “what if” impact analysis to simulate many partition configurations
  • Automatic conversion of gated clocks and netlist optimization
  • Clock Domain Crossing (CDC) analyzer and timing constraints editor
  • Board-level connecting resources awareness, global clocks and traces, LVDS, single-ended
  • Automatic insertion of Inter-Chip-Connection (ICC) buses
    • Use SERDES modules
    • LVDS or single-ended signalling
    • Direct routing or global traces
  • Quick check-list generation for comprehensive validation of partitioning decisions
  • Post-partitioning simulation support

 

Scalability and Reuse

Enabling scalability is the core objective of the HES-DVM™ development team, and this is what makes our solution unique. The FPGA technology is evolving so fast that it is wise to be always on the cutting edge. Instead of being limited to a fixed dedicated hardware emulation platform, Aldec continues to develop an open architecture that can be quickly migrated to the next generation FPGA technology, and also used with custom in-house made prototyping boards.

  • Scalable across FPGA technology, quick adoption of newest FPGA
  • Supports scalable hardware platforms with backplane or extension slots
  • Scalable for increasing design sizes with incremental and parallel synthesis and implementation
  • Supports scalable simulation acceleration and emulation clusters
  • Reuse the same hardware across different teams: simulation, emulation, prototyping
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