Aldec Blog/News RSS Feed https://www.aldec.com Aldec News RSS Feed News: 2017-03-15 https://www.aldec.com/en/company/news/2017-03-15/332 https://www.aldec.com/en/company/news/2017-03-15/332 Wed, 15 Mar 2017 00:00:00 -0700 Aldec Celebrates 10 Years in DO-254 at Certification Together International Conference News: 2017-03-07 https://www.aldec.com/en/company/news/2017-03-07/331 https://www.aldec.com/en/company/news/2017-03-07/331 Tue, 07 Mar 2017 00:00:00 -0800 Aldec Introduces End-to-end HW/SW Co-verification for Xilinx Zynq SoC FPGAs at Embedded World 2017 News: 2017-02-28 https://www.aldec.com/en/company/news/2017-02-28/330 https://www.aldec.com/en/company/news/2017-02-28/330 Tue, 28 Feb 2017 00:00:00 -0800 Aldec unveils Xilinx UltraScale FPGA-based prototyping board enabling Simulation Acceleration and Emulation with the latest release of HES-DVM News: 2017-02-23 https://www.aldec.com/en/company/news/2017-02-23/329 https://www.aldec.com/en/company/news/2017-02-23/329 Thu, 23 Feb 2017 00:00:00 -0800 Aldec to Demonstrate UVM Simulation Acceleration with Network-On-Chip (NoC) Demo Design at DVCon U.S. 2017 News: 2017-02-21 https://www.aldec.com/en/company/news/2017-02-21/328 https://www.aldec.com/en/company/news/2017-02-21/328 Tue, 21 Feb 2017 00:00:00 -0800 Aldec to Showcase FPGA Acceleration of Genome Alignment, Motion Detection and Face Detection Algorithms at isFPGA 2017 Blog: 2017-02-14 https://www.aldec.com/en/company/blog/131--key-components-of-effective-rtl-linting-and-cdc-verification https://www.aldec.com/en/company/blog/131--key-components-of-effective-rtl-linting-and-cdc-verification Tue, 14 Feb 2017 00:00:00 -0800 Key Components of Effective RTL Linting and CDC Verification News: 2017-02-14 https://www.aldec.com/en/company/news/2017-02-14/326 https://www.aldec.com/en/company/news/2017-02-14/326 Tue, 14 Feb 2017 00:00:00 -0800 Aldec sets a new paradigm with a single platform for Design Rule Checking and Clock Domain Crossing Verification for FPGA and ASIC designs News: 2017-02-01 https://www.aldec.com/en/company/news/2017-02-01/325 https://www.aldec.com/en/company/news/2017-02-01/325 Wed, 01 Feb 2017 00:00:00 -0800 Aldec delivers DO-254 Compliant Templates and Checklists with the latest release of Spec-TRACER News: 2017-01-19 https://www.aldec.com/en/company/news/2017-01-19/324 https://www.aldec.com/en/company/news/2017-01-19/324 Thu, 19 Jan 2017 00:00:00 -0800 Aldec provides Finite State Machine Coverage for verification of safety-critical FPGAs News: 2016-12-07 https://www.aldec.com/en/company/news/2016-12-07/318 https://www.aldec.com/en/company/news/2016-12-07/318 Wed, 07 Dec 2016 00:00:00 -0800 Top Aldec Design and Verification Blog Articles from 2016 News: 2016-11-16 https://www.aldec.com/en/company/news/2016-11-16/317 https://www.aldec.com/en/company/news/2016-11-16/317 Wed, 16 Nov 2016 00:00:00 -0800 Aldec delivers significant SystemVerilog speedup and a pioneering initiative for VHDL users with latest Riviera-PRO News: 2016-11-14 https://www.aldec.com/en/company/news/2016-11-14/319 https://www.aldec.com/en/company/news/2016-11-14/319 Mon, 14 Nov 2016 00:00:00 -0800 SemiWiki: 3 in 1 Hardware Verification Blog: 2016-11-14 https://www.aldec.com/en/company/blog/130--an-easier-path-to-faster-c-with-fpgas https://www.aldec.com/en/company/blog/130--an-easier-path-to-faster-c-with-fpgas Mon, 14 Nov 2016 00:00:00 -0800 An Easier Path to Faster C with FPGAs News: 2016-11-14 https://www.aldec.com/en/company/news/2016-11-14/316 https://www.aldec.com/en/company/news/2016-11-14/316 Mon, 14 Nov 2016 00:00:00 -0800 Aldec and Indian Institute of Science faculty enterprise, ReneLife, showcase ReneGENE for accurate genome alignment on HES Accelerator at SC16 News: 2016-11-10 https://www.aldec.com/en/company/news/2016-11-10/315 https://www.aldec.com/en/company/news/2016-11-10/315 Thu, 10 Nov 2016 00:00:00 -0800 Aldec adds largest Xilinx UltraScale to latest HES Solution for FPGA Simulation Acceleration, Emulation, and Prototyping to be unveiled at SemIsrael 2016 Blog: 2016-11-10 https://www.aldec.com/en/company/blog/129--fpga-vhdl-verification https://www.aldec.com/en/company/blog/129--fpga-vhdl-verification Thu, 10 Nov 2016 00:00:00 -0800 FPGA VHDL Verification Blog: 2016-11-09 https://www.aldec.com/en/company/blog/128--beer-cars-and-verification https://www.aldec.com/en/company/blog/128--beer-cars-and-verification Wed, 09 Nov 2016 00:00:00 -0800 Beer, Cars, and Verification News: 2016-10-27 https://www.aldec.com/en/company/news/2016-10-27/322 https://www.aldec.com/en/company/news/2016-10-27/322 Thu, 27 Oct 2016 00:00:00 -0700 Semiconductor Engineering: Emulation’s Footprint Grows News: 2016-10-27 https://www.aldec.com/en/company/news/2016-10-27/320 https://www.aldec.com/en/company/news/2016-10-27/320 Thu, 27 Oct 2016 00:00:00 -0700 Semiconductor Engineering: Too Big To Simulate? Blog: 2016-10-24 https://www.aldec.com/en/company/blog/127--leveraging-the-power-of-vdma-engines-for-computer-vision-apps-with-tysom-part-2 https://www.aldec.com/en/company/blog/127--leveraging-the-power-of-vdma-engines-for-computer-vision-apps-with-tysom-part-2 Mon, 24 Oct 2016 00:00:00 -0700 Leveraging the Power of VDMA Engines for Computer Vision Apps with TySOM™ - Part 2