Aldec launches ALINT-PRO-CDC™ delivering comprehensive CDC Verification Strategies for SoC and FPGA Designs
Henderson, NV – January 29, 2015 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, announces the release of ALINT-PRO-CDCTM 2015.01. This latest design verification solution from Aldec enables verification of clock domain crossings and handling of metastability issues in complex, modern multi-clock designs.
“Metastability issues can be easily overlooked during conventional functional verification flow, leading to random design failures in the field,” said Pavlo Leshtaiev, Product Manager, Aldec Software Division. “Having a specialized verification tool is a must for the modern ASIC/FPGA designer to achieve high performance and quality. ALINT-PRO-CDC uncovers critical problems during the RTL Design and Functional Verification stages, significantly cutting down time to market.”
ALINT-PRO-CDC offers a verification strategy comprised of three key elements: Static Structural Verification, Design Constraints Setup, and Dynamic Functional Verification.
Static Structural Verification Static analysis includes automatic detection of clocks and resets, asynchronous clock domains and crossings between them. Crossings are checked to confirm proper synchronization and verified against best practices. Well-designed GUI framework provides intuitive interface and offers efficient issues analysis, including graphical representation of synthesized netlist and clocks, as well as reset viewer, elaboration viewer, etc.
Design Constraints Setup Based on the clock networks analysis and combinational paths between design ports and synchronous cell pins ALINT-PRO-CDC can create the initial SDC file to facilitate design setup. The tool also offers custom extension to design constraints, which allows describing non-synthesizable modules and custom synchronizers resulting in precise linting violations.
Dynamic Functional Verification (Riviera-PROTM integration) ALINT-PRO-CDC presents automatic SystemVerilog testbench generation, which enables metastability insertion in regular simulation-based verification flow. Testbench also provides a set of assertion and coverage statements to check synchronizers usage correctness and verify that clock domain crossings are covered.
ALINT-PRO-CDC 2015.01 is available today. For additional information or to request a free evaluation download, visit www.aldec.com/Products/ALINT-PRO-CDC.
Aldec Inc., established in 1984 and headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com
Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are the property of their respective owners.
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