Aldec Delivers Support for Test Ranking in Code Coverage Analysis

Date: Mar 10, 2015
Type: Release

Henderson, NV – March 10, 2015 – Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for FPGA and ASIC devices, announces the availability of a new version of its mixed-language, advanced functional verification platform, Riviera-PRO™ 2015.02. This release enhances code coverage analysis with added Test Ranking capabilities. These newest features enhance the already robust, UCIS-compatible coverage database in Riviera-PRO, which supports collecting coverages under one database file, as well as merging, reporting and verification plan linking. With the addition of Test Ranking with code coverage analysis, Riviera-PRO now offers a complete solution for measuring the usability of test cases under code coverage metrics.


"Test Ranking allows a user to compare a single coverage result against all others to determine its usability and to classify the results based on the contribution of the tests to the total code coverage score,” said Satyam Jani, Riviera-PRO Product Manager. “Along with parameters such as weight, goal, and limitations, the user can also leverage cost parameters such as simulation or CPU time. This allows verification engineers to focus on test runs which yield the greatest code coverage value in the shortest amount of time.                                                                                                                                          Fig. 1 Test Rank results shown in Riviera-PRO™


Riviera-PRO 2015.02 enables the ultimate testbench productivity, reusability, and automation by combining a high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards. The latest release includes numerous new features, enhancements, performance optimizations and is available today.


For a free evaluation download, tutorials, and What’s New Presentation, visit or contact


About Aldec

Established in 1984 and headquartered in Henderson, Nevada, Aldec, Inc. is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions.


Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are the property of their respective owners.

Media Contact: Aldec, Inc.                               
Christina Toole, Corporate Marketing Manager
+ (702) 990-4400
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