Aldec Introduces Hybrid Emulation with ARM® Fast Model Support

Date: Oct 27, 2015Type: Release

Henderson, NV – October 27, 2015 - Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, is introducing Hybrid Emulation including support for ARM® Fast Models. Announcing their new and easy-to-use capability to link an SoC emulation hardware platform with a virtual platform, Aldec is enabling FPGAs and SystemC models to work together to provide greater productivity and reduce time-to-market for embedded software in today’s SoC projects.

The two major components at the heart of Hybrid Emulation are the HES-7™ platform from Aldec, and Fast Models from ARM®, each providing leading edge capability to the combined solution.

HES-7 is so named because it is Aldec’s seventh generation Hardware Emulation Solution, based upon Xilinx® FPGAs and fully integrated into Aldec’s Design Verification Manager (DVM). The HES‑DVM™ suite is available in configurations using Virtex-2000T or Ultrascale-440 devices, offering the largest FPGA resource available on a single board, and over one billion ASIC gates in multi-board configurations.Virtual Prototype Employing ARM Fast Models

ARM Fast Models provide those developing software for ARM-based SoCs with the earliest possible target platform for test and validation. Use either in stand-alone fixed model form, or in conjunction with ARM’s DS-5 Development System, ARM Fast Models are assembled into a full transaction-level representations of a CPU subsystem; providing a virtual platform that allows high-level software to run at near full speed.

Software is often the make-or-break of an SoC-based product”, says Aldec Hardware Division General Manager, Zibi Zalewski. “It is critical that developers have the best possible chance to test software in the context of the final system. ARM Fast models allow that for the top of the software stack, and emulation allows it for the hardware-dependent software at the base of the stack. With Hybrid Emulation we can combine these methods into a whole-stack approach.”

With software-hardware integration often sitting in the critical path of an SoC project, hybrid emulation allows both software and hardware teams to work on the most up-to-date version of the project, long before first silicon is available, or even much of the RTL or IP has been completed.

The connection between the virtual platform and the Emulator is provided by Verification IP (VIP) from Aldec which includes transaction-level model (TLM) adaptors, plus Bus Functional Models (BFMs) and hardware transactors compliant with the Standard Co-emulation Model Interface (SCE-MI). The VIP may also be used to link to other complementary simulation environments including UVM verification and external SystemC test-benches. “By adopting the SCE-MI standard, rather than a closed proprietary approach adopted elsewhere, we and our customers are able to work with ARM and other model and tool suppliers more easily” remarks Zalewski.

Aldec will be demonstrating this new Hybrid Emulation capability at ARM TechCon in Santa Clara, CA on 11th and 12th November.



All you need to use hybrid emulation; HES-DVM, the necessary SCE-MI interfaces, and the Fast Models are available today from Aldec and ARM. To learn more about hybrid emulation or to evaluate, please contact sales@aldec.com or call us at (702) 990-4400 or via our worldwide distribution partners.


About Aldec Hardware Emulation Solutions (HES)

HES-7™ provides SoC/ASIC hardware verification and software validation teams with a high-performance, scalable, and multi-purpose FPGA-based platform. HES-7, including HES-DVM, is used in labs worldwide for tasks including simulation acceleration, emulation, hybrid virtual prototypes, co-emulation, high-speed prototyping, and software validation at MHz speeds. Learn more about Aldec Hardware Emulation Solutions.


About Aldec

Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Emulation, Design Rule Checking, Clock Domain Crossing, VIP Transactors, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com


 Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are the property of their respective owners.

Media Contact: Aldec, Inc.                               
Christina Toole, Corporate Marketing Manager
+ (702) 990-4400
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