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Aldec delivers significant SystemVerilog speedup and a pioneering initiative for VHDL users with latest Riviera-PRO

Date: Nov 16, 2016Type: Release

Henderson, NV – November 16, 2016 – Aldec, Inc., today announced the latest release of Riviera-PRO™ 2016.10 Advanced Verification Platform. Riviera-PRO is a tightly integrated solution for functional verification of complex System on Chip (SoC), ASIC and FPGA designs. This new release of Riviera-PRO brings significant performance improvements in SystemVerilog compilation and simulation, with some areas such as random constraint simulating up to 35% faster.

In response to customer needs, Riviera-PRO now also offers a complementary solution for Metric Driven Verification in Open Source VHDL Verification Methodology (OSVVM) for OSVVM users with the need to collect functional verification data.

“The engineering community often requires solutions that are not strictly connected with a particular vendor, and for this reason Aldec strives to deliver solutions that fill in gaps between open source solutions and ours,” said Radek Nawrot, Riviera-PRO Product Manager. “In addition to close integration with open source solutions, Riviera-PRO 2016.10 also provides additional debugging tools for functional verification to support our users and shorten their time to market.”

Along with introducing official support for DPI-SC interface, Riviera-PRO 2016.10 also introduces new debugging tools for Finite State Machines, FSM List, which allows users to easily validate the structure of FSM and correlate it with test suite metrics.

The 2016.10 release of Riviera-PRO also includes numerous new features, enhancements, and performance optimizations. For additional information, tutorials, free evaluation download and What’s New Presentation, visit http://www.aldec.com/Products/Riviera-PRO.

 

About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, , CDC Verification, IP Cores, Embedded, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. http://www.aldec.com/

Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are the property of their respective owners.

 

Media Contact:          
Christina Toole, Aldec, Inc.                             
+ (702) 990-4400
christinat@aldec.com

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