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Aldec offers Advanced Screening of Functional Verification Platform’s Latest Release at DVCon 2013

Date: Feb 26, 2013Type: Release

Henderson, NV – February 26, 2013 – Aldec, Inc., joins other top tier functional design and verification exhibitors at The Design & Verification Conference & Exhibition (DVCon), February 25-28, 2013 in San Jose, California.

 

“With its consistent focus on delivering the latest information from the leading edge of technology, standards and methods, DVCon continues to serve as an important platform to bring new solutions market,” said Christina Toole, Aldec Marketing Manager, “We are pleased to be back in San Jose again this year with an advanced preview of our latest solutions.”

 

Advanced Verification

Aldec will offer an early preview of the latest version of its functional verification platform, Riviera-PRO™, delivering solutions to verification challenges. Demonstrations will showcase the innovative tool suite, including requirement-driven design, simulation, and debugging for mixed-language and mixed-signal SoC and large-scale FPGA designs. The platform’s latest release includes significant enhancements for efficient application of Universal Verification Methodology (UVM), verification management and coverage closure with UCIS-compatible database, and mixed VHDL, Verilog-AMS, SystemVerilog, and SystemC designs. www.aldec.com/products/riviera-pro 

 

Hardware-assisted Verification

DVCon attendees will also learn about the latest HES™ innovations. HES-DVM™ is Aldec’s complete ASIC/SoC hardware-based verification solution that provides a unified platform for bit level simulation acceleration, transaction level emulation, HW/SW co-verification, virtual modeling and prototyping. www.aldec.com/products/hes-dvm

 

Free UVM and Assertions Online Training

Aldec invites visitors to DVCon to tour Fast Track™ ONLINE, a convenient, online training portal that is available at no cost to the design verification community. The premiere training course for the new program is, Fast Track™ to UVM ONLINE, which introduces hardware designers familiar with Design Subset of SystemVerilog into the brave, new world of Universal Verification Methodology (UVM). Newly added, Fast Track™ to Assertions ONLINE, includes practical examples of assertions and covers presented side-by-side for VHDL (PSL) and SystemVerilog (SVA). www.aldec.com/onlinetraining.

 

About DVCon

DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. For more on Accellera, visit www.accellera.org. For more on DVCon, visit www.dvcon.org.

 

About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, ASIC Prototyping, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com


Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.

Media Contact: Christina Toole,
Aldec, Inc.
+(702.990.4400)
christinat@aldec.com
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