Aldec to Showcase FPGA Acceleration of Genome Alignment, Motion Detection and Face Detection Algorithms at isFPGA 2017
Henderson, NV – February 21, 2017 – Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification solutions for FPGAs and ASICs today announced that it will showcase FPGA-based acceleration of several state-of-the-art algorithms such as Genome Short Reads Alignment, Object Movement Detection and Face Detection at isFPGA 2017 to be held in Monterey, California from February 22-24, 2017.
Visitors to Aldec’s Booth at isFPGA will have the opportunity to view the following demonstrations:
- Genome Short Reads Alignment Aldec to present AccuRA™, a high-performance reconfigurable FPGA accelerator engine for Renelife® ReneGENE™, offered on Aldec HES-HPC™ for accurate, and ultra-fast big data mapping and alignment of DNA short-reads from the Next Generation Sequencing (NGS) platforms. AccuRA demonstrates a speedup of over ~ 1500+ x compared to standard heuristic aligners in the market like BFAST which was run on an 8-core 3.5 GHz AMD® FX™ processor with a system memory of 16 GB. AccuRA employs a scalable and massively parallel computing and data pipeline, which achieves short read mapping in minimum deterministic time. It offers full alignment coverage of the genome (million to billion bases long), including repeat regions and multi-read alignments.
- Object Movement Detection reference design based on ViBe™ Background Subtraction algorithm and HES-HPC™ FPGA-based Accelerator running @1280x720, 30fps . The image processing background subtraction techniques are utilized to transform and detect moving objects in recorded video. HES-HPC™ platform provides performance enhancement by utilizing extreme parallel processing capabilities of FPGAs to execute computationally intensive image transformations.
- Face Detection reference design based on TySOM-2-7Z045 EDK + TySOM-2-ADAS-FMC. Real time streaming video @1280x720, 30fps captured by an HDR-CMOS image sensor and processed by a Xilinx Zynq-7000 SoC FPGA which contains a high performance dual-core ARM Cortex-A9 processing system with FPGA fabric. In order to achieve the goal for real-time processing performance, the most computational intensive parts of the code are off-loaded from ARM Cortex-A9 to FPGA part of Zynq device using Xilinx SDSoC™ tool. The accelerated part includes edge detection, colorspace conversion and frame merging tasks.
Scalable FPGA-based accelerators with the latest low power, Xilinx® Kintex-Ultrascale™ FPGA providing outstanding computational capabilities with power efficiency not achievable with GPU-based accelerators. HES-HPC includes Kintex-UltraScale XCKU085 / XCKU115 providing up to 1,451K Logic Cells & 5,520 DSPs, Zynq-7000, Host PHY (PCI Express x8, USB, Ethernet), 2x DDR4 16GB, 4x RLD3 576Mb, PCIe, 2x QFSP+, USB 3.0, SATA, 2x Samtec Firefly, ADC/DAC. Aldec provides custom engineering services for RTL porting and optimization for HPC applications. Additionally, based on Aldec’s 30+ years expertise in FPGA/ASIC verification, Aldec provides RTL bring-up environment and porting services.
The TySOM™ EDK is for the embedded designer who requires high-performance RTL simulation/debugging for embedded applications such as IoT, Embedded Vision, UAV, and Automotive. The TySOM kit includes Riviera-PRO™ Advanced Verification Platform and a Xilinx® Zynq™ development board that contains a single Zynq chip (FPGA + Dual ARM® Cortex-A9), memories (DDR3, uSD), communication interfaces (miniPCIe, Ethernet, USB, Pmod, JTAG) and multimedia interfaces (HDMI, audio, CMOS camera).
Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification, Embedded Solutions and Military/Aerospace solutions.
Christina Toole, Aldec, Inc.
+ (702) 990-4400