Hardware Emulation Solutions HES-DVM™ is a hybrid verification and validation ecosystem for hardware and software teams developing the latest SoC and ASIC designs. Partnering the latest high-capacity FPGA technology with industry leading co-emulation standards, HES-DVM allows for multiple modes of verification and validation including: Simulation Acceleration Co-emulation and Virtual Modeling In-Circuit Emulation Embedded Software and Hardware Co-verification Aldec integrates five main elements within HES™ to provide best-in-class hardware emulation solutions. FPGA Prototyping Hardware Reuse prototyping boards utilizing the latest Xilinx® Virtex™ 7 FPGAs for hardware emulation up to 96M ASIC gates with scalable backplane. The HES-7™ prototyping platform incorporates 25 Gb/s non-proprietary backplane connectors for high-speed data transmission, up to 16GB of DDR3 memory, PCI-Express connection to host PC, and an array of media interface peripherals. In addition to supporting emulation with off-the-shelf boards, HES-DVM™ can be utilized with in-house developed FPGA prototyping boards. Design Verification Manager (DVM) Fully automated and scriptable design environment which facilitates the design setup for simulation acceleration, emulation and virtual modeling with FPGA prototyping Hardware. HES-DVM™ contains features such as ASIC to FPGA conversion, automatic design partitioning, embedded memory mapping, clock conversions and integration to 3rd party tools like simulators, virtual platforms hardware and software debugging front-ends. Verification Interfaces HES™ integrates various hardware/software verification interfaces utilizing the latest co-emulation standards. Transaction level testbenches utilizing UVM or similar methodology can use the SCE-MI for seamless connection of simulator with emulator for simulation acceleration. Virtual models of SoC, peripherals, or processors like ARM® Cortex™ can be co-emulated utilizing TLM interface. Real-time peripherals can be connected via speed adapters enabling in-circuit emulation. Verification IP A complete emulation eco-system must contain a comprehensive library of firm Verification IP (VIP). The availability of transactors, drivers, monitors and speed-adapters of industry leading bus protocols like AMBA AHB, AXI or communication peripherals like USB, PCIe, Ethernet is key to the quick building of a reliable design verification environment and successful deployment of emulation. Aldec provides ready to use VIPs proven in SoC designs that have been already taped-out after successful verification. Aldec’s best experts in the field are ready to develop other VIPs or to assist users with the process. Debugging Tools HES™ features an array of debugging capabilities such as true RTL view with complete design visibility, memory view/modify, triggering, breakpoints and clock step control. The true RTL view means that all debug probes are saved, preserving original signals’ names, data types and hierarchy. A choice of different waveform formats like ASDB or FSDB allows for integration with either Aldec or 3rd party tools. All debugging functions can be used either within HW Debugger tool or in the testbench via dedicated HES Debug API, with both offering remote access capability via TCP-IP.