Aldec Introduces End-to-end HW/SW Co-verification for Xilinx Zynq SoC FPGAs at Embedded World 2017
Nuremberg, Germany - March 7, 2017 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, introduces end-to-end HW/SW Co-Verification for Xilinx® Zynq® SoC FPGAs with ARM® Cortex® A-9 at Embedded World 2017 to be held March 14-16, 2017, in Nuremberg, Germany.
The solutions starts with HW/SW co-simulation of applications and drivers emulated on open-source QEMU ARM processor together with HDL executed on Riviera-PRO™. Zynq designers are able to setup hardware breakpoints in Riviera-PRO and/or software breakpoints in QEMU and perform concurrent debugging of drivers, kernels, and HDL using GDB debugger and Riviera-PRO. After few successful co-simulation runs of the processor sub-system with the FPGA fabric, the TySOM Zynq board is used for final SoC chip validation.
“Integration and simulation of FPGA custom IPs with QEMU is now simplified with the addition of Aldec QEMU Bridge that connects QEMU and Riviera-PRO,” said Radek Nawrot, Software Product Manager. “The QEMU Bridge converts SystemC TLM transactions to AXI and vice versa providing a fast interface for co-simulation.”
“Instead of using simplified BFMs of the ARM processor with limited functionality, Zynq designers are able to use QEMU ARM emulator that uses dynamic binary translation to achieve accurate execution and fast emulation speed,” said Louie De Luna, Director of Marketing. “Both software and hardware teams are now able to work on a single environment for simulation and SoC chip validation without the need of rerunning a significant number of FPGA implementation runs. This streamlines verification needed for today’s fast-evolving embedded designs.”
“The complete TySOM™ product line with FMC daughter cards and professional reference designs targeting Embedded Vision, IoT, and Software Defined Radio will be showcased at Embedded World 2017,” said Zibi Zalewski, General Manager Hardware Division. “Our Zynq boards together with reference designs include easy-to-follow tutorials providing the ideal embedded development platform with a clear path to production.”
Visitors to Aldec’s Booth at Embedded World 2017 will have the opportunity to view the following end-to-end HW/SW co-verification flows using QEMU, Riviera-PRO and TySOM Zynq board portfolio:
- QEMU flow for HW/SW co-simulation reference design based on MIPI CSI-2 HDL core. The application running on Linux on QEMU ARM-Cortex A-9 stimulates the MIPI CSI-2 HDL core running in Riviera-PRO through the Aldec QEMU Bridge and AXI BFM. Sample HW/SW breakpoints are inserted so that concurrent debugging is enabled using GDB debugger and Riviera-PRO.
- ADAS Multi-Camera Surround View reference design based on TySOM-2-7Z045 EDK + FMC-ADAS + FMC-Vision. The reference design captures, processes and displays 4 simultaneous First Sensor® Blue Eagle™ camera video streams in real-time. In order to achieve the goal for real-time processing performance, the most computational intensive parts of the code are off-loaded from ARM Cortex-A9 to FPGA part of Zynq device using Xilinx SDSoC™ tool. The accelerated part includes edge detection, colorspace conversion and frame merging tasks.
- IoT Gateway reference design based on TySOM-1-7Z030 EDK. The reference design runs on the core of Embedded Linux Host that provides Internet LAN or WAN (wired or Wi-Fi connection) and handles cloud protocols designated for IoT applications such as MQTT protocol used by the Amazon Web Services (AWS). The IoT Gateway supports multiple wireless and wired protocols used to build Personal Area Networks (PAN) comprising of Edge layer devices including Bluetooth, Z-wave, ZigBee, Wi-Fi and USB.
- Face Detection reference design based on TySOM-2-7Z045 EDK + FMC-ADAS. Real time streaming video @1280x720, 30fps captured by an HDR-CMOS image sensor and processed by a Xilinx Zynq-7000 SoC FPGA which contains a high performance dual-core ARM Cortex-A9 processing system with FPGA fabric. In order to achieve the goal for real-time processing performance, the most computational intensive parts of the code are off-loaded from ARM Cortex-A9 to FPGA part of Zynq device using Xilinx SDSoC™ tool. The accelerated part includes edge detection, colorspace conversion and frame merging tasks.
The TySOM™ EDK is for the embedded designer who requires high-performance RTL simulation/debugging for embedded applications such as IoT, Embedded Vision, UAV, and Automotive. The TySOM kit includes Riviera-PRO™ Advanced Verification Platform and a Xilinx® Zynq™ development board that contains a single Zynq chip (FPGA + Dual ARM® Cortex-A9), memories (DDR3, uSD), communication interfaces (miniPCIe, Ethernet, USB, Pmod, JTAG) and multimedia interfaces (HDMI, audio, CMOS camera).
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification, Embedded Solutions and Military/Aerospace solutions. http://www.aldec.com/
Christina Toole, Aldec, Inc.
+ (702) 990-4400