Chip Design: CDC Verification: Using Both Static and Dynamic Checking is Key to Success

Date: May 13, 2015
Type: In the News

by Pavlo Leshtaiev


Clock domain crossing (CDC) verification has become a critical element for success in modern digital electronic designs.  Unlike “the old days” when relatively simple and slow digital designs could be run on a single synchronous clock, today’s complex, high-speed designs use multiple asynchronous clocks to drive separate high-frequency logic sections.  The CDC challenges come into play where these separate clock domains interface because any weaknesses in the crossing design can result in data errors, control problems or even overall system failure.


For the rest of this article, please visit Chip Design.

Ask Us a Question
Ask Us a Question
Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.
We use cookies to ensure we give you the best user experience and to provide you with content we believe will be of relevance to you. If you continue to use our site, you consent to our use of cookies. A detailed overview on the use of cookies and other website information is located in our Privacy Policy.