Chip Design: CDC Verification: Using Both Static and Dynamic Checking is Key to SuccessDate: May 13, 2015 Type: In the Newsby Pavlo Leshtaiev Clock domain crossing (CDC) verification has become a critical element for success in modern digital electronic designs. Unlike “the old days” when relatively simple and slow digital designs could be run on a single synchronous clock, today’s complex, high-speed designs use multiple asynchronous clocks to drive separate high-frequency logic sections. The CDC challenges come into play where these separate clock domains interface because any weaknesses in the crossing design can result in data errors, control problems or even overall system failure. For the rest of this article, please visit Chip Design.
