Aldec solves ASIC design partitioning challenges with HES-DVM Proto mode

Date: Sep 11, 2017
Type: Release

Henderson, Nevada, U.S.A. – September 11, 2017 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has unveiled the latest release of its HES-DVM™ software, bringing a new Prototyping mode in addition to Simulation Acceleration and Emulation modes.


HES DVM Graphic

The new HES-DVM Proto introduces new design partitioning and partition interconnection tools; designed to meet the growing demands of FPGA prototyping and verification engineers who need to find the ideal balance between automation and controllability of the partitioning process; in order to achieve the highest clocks frequency while running designs in complex multi-FPGA prototyping platforms.


With the 2017.09 release of HES-DVM™ users will be able to quickly evaluate various partitioning scenarios and choose the one which achieves the best performance on a given prototyping board. The convenient GUI visualization and impact analysis tool shows required and available interconnections so that bottlenecks can be identified quickly and fixed, either by improving partitioning or customizing the board.


Common multi-FPGA partitioning challenges in regards to limited I/O and board-level interconnections have been solved in the latest release of HES-DVM™. Aldec achieved this through facilitating the automatic insertion of configurable Inter-Chip Connection modules that utilize SERDES modules and LVDS signaling to achieve the highest possible transmission speeds of contemporary FPGAs. Additionally, the automatic conversion of gated clocks facilitates reliable implementation of ASIC designs in FPGA.


The new HES-DVM Proto mode supports Aldec HES Prototyping Platform as well as any third party boards that utilize Virtex-7™ or Virtex UltraSCALE™ FPGAs.


“We are excited to announce this HES-DVM Proto release because it complements our FPGA Prototyping and Emulation solutions, with the features that facilitate setting up designs as multi-FPGA prototypes, and potentially saving months of tedious work.” said Zibi Zalewski, General Manager of Hardware Division. “We are the only EDA Company who uses the FPGA technology so effectively - the same FPGA prototyping boards can be used for simulation acceleration, co-emulation with virtual platforms and now much easier for physical prototyping.”


To learn more, register to Aldec’s upcoming webinar: Aiding ASIC Design Partitioning for multi-FPGA Prototyping



The new HES-DVM™ 2017.09 software is available now. To learn more or to evaluate, visit, e-mail, call +1 (702) 990-4400, or contact our worldwide distribution partners.


About HES™ Prototyping

Aldec offers a portfolio of HES™ prototyping boards based on the largest Xilinx FPGA of the Virtex UltraScale and Virtex-7 families. The boards are architected to allow for easy expansion using BPX backplane and standardized FMC and BPX daughter card connectors.


About HES-DVM™

HES-DVM™ is a fully automated and scalable hybrid verification environment for SoC and ASIC designs.  Utilizing the latest co-emulation standards like SCE-MI or TLM and the newest FPGA technology, hardware and software design teams obtain early access to the hardware prototype of the design. HES-DVM is used in labs worldwide for all kinds of emulation and physical prototyping tasks including Simulation Acceleration, Hybrid Virtual Prototypes, In-Circuit Emulation, Software Validation and Prototyping.


About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions.

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