The latest in SoC and ASIC Prototyping News, Events and Resources
The latest in SoC and ASIC Prototyping News, Events and Resources – March 2013
Building an Efficient Clock Network for FPGA-Prototyping Boards
Developing an in-house prototyping board requires a large investment in time, knowledge, and resources. Going down the “build-your-own” route does, however, provide advantages such as: the ability to add personalized interfaces, manufacture the board for different goals (speed, power, flexibility), and reduced Read more
cost compared to buying an off-the-shelf board. One large issue designers face is developing an efficient clock network from resources available on the FPGAs and board-level clock resources which will provide flexibility to designers.
On-Board Clock Resources
Modern FPGAs provide an array of clock resources such as PLLs for scaling of clock frequencies and multiple clock domains, however this is only helpful for systems which are able to fit into a single chip. Today’s SoC’s are not always able to fit onto a single FPGA and must be partitioned across several to fit onto a prototyping environment. Multiple FPGA boards require a full hierarchy of clocking functionality such as clock multiplexers, divers and multipliers, board clock synchronization, and board-level clock input. There are techniques to cut down on the complexity of the task such as gated clock conversions. ASIC designs typically implement gated clocks to cut down on the switching activity of the system clock, greatly reducing power. However, this does not translate well in the FPGA environment which would require clock enables instead of gates clocks, which can present timing issues.
Designing a flexible clock network requires a close look at system requirements which may include:
1. Matching clock delays
Each of these requirements is a large task upon itself, in which the designer may include multiple clock elements such as source selectors, special high-speed clocks (GTX links), external clock sources, and scalars to solve multiple issues while providing flexibility. It may be tempting to some designers to develop a board specifically for clock resources to simply the complexity, which increase design can cost and silicon real-estate. However, a board without an adequate amount of flexibility places a greater restriction on the partitioning decisions more large designs.
HES-7 Configurable Clock Resources
The HES-7 clock scheme is comprised of low-skew global clock networks with user programmable PLLs and MMCX clock connectors. Included on the board are five clock oscillators ranging from 192 MHz to 500 MHz, and external differential clock inputs up to 450 MHz. To provide global clock connection to the board, five global clock inputs are provided via backplane connector (capable of speeds up to 25 GB/s). Dedicate clock circuitry is allocated for the GTX lines and PLL module to simplify signal configuration. Both clock schemes shown above below for GTX lines and PLL module.
Figure 1: CLK_GTX clocking scheme block diagram
Figure 2: CLK_PLL clocking scheme block diagram
For Technical Specifications and more on the HES-7 ASIC Prototyping Platform, visit www.aldec.com/products/prototyping/hes-7.
Aldec in the Classrooms of Today's Top Engineering Universities
Aldec’s University Program is committed to providing future engineers with world-class tools for their digital system designs and verification methodologies. These tools are offered at a lower cost to educational facilities who meet the university program requirements. In addition, students are able to download Read more
the Free Active-HDL Student Edition which allows them to use the design entry and simulation tool throughout their coursework.
Students and faculty are also provided with access to online resources such as whitepapers, webinars, and demonstrations. Aldec takes pride in its commitment to tomorrow’s engineers, and often sends engineers to deliver onsite presentations to students and faculty on the latest research in the field of system verification. Aldec recently presented as part of the VLSI Design & Test Seminar Series by Auburn University. This series seeks to provide an open forum for various faculty, graduate and undergraduate students with research and development efforts in the area of design and test of VLSI systems, including application specific and programmable circuits in digital, analog, and mixed-signal microsystems.
Aldec visited Auburn University this past month for a seminar on a paper to be presented during this year’s Military and Aerospace Programmable Logic Devices (MAPLD) conference. The paper titled, “Hybrid Platform for High Capacity FPGA Validation and Verification”, showcases the Hardware Emulation Solution (HES) ecosystem, a complete validation and verification platform for large capacity SoC and ASIC designs. During the visit, Aldec Research Engineer and Auburn graduate, Bill Jason Tomas, presented different modes of validation and verification including: simulation acceleration, prototyping, and transaction level emulation. Tomas also presented many debugging capabilities of Aldec’s hardware emulation application, HES-DVM, to quickly debug and diagnose system-level faults occurring in a design.
Tomas also visited digital design classrooms to showcase Aldec’s FPGA design and verification tools, Active-HDL and Riviera-PRO. In these demonstrations, Tomas utilized examples from classroom activities and displayed how students can utilize Aldec tools to develop, debug, and verify their own digital systems.
“It was a great experience giving back to my alma mater, and providing them with tools which will help them with their studies”, stated Tomas during an interview with faculty.
ARM Cortex SoC Prototyping Platform for Industrial Applications
Modern industrial systems are faced with many key design challenges including: system complexity, real-time performance requirements, evolving standards, and rising costs. ASIC prototyping platforms, such as the Aldec HES-7, provide a platform for designers to implement and verify functionality of Read more
industrial systems at-speed prior to silicon tape-out, saving money from costly re-spins. In this white paper, we take a look how to tackle a few industrial design applications with Aldec’s HES-7, which now supports ARM Cortex-A9 based designs by leveraging Xilinx’s new Zynq All Programmable SoC.
Download white paper: ARM Cortex SoC Prototyping Platform for Industrial Applications
View recorded webinar: ARM Cortex SoC Prototyping Platform for Industrial Applications
Figure 1: Advantage of Building an Industrial Network Application Using Partial-Reconfiguration
SoC and ASIC Prototyping
Technical Article:New Electronics: ASIC/SoC Prototyping Platforms Increase Productivity
Recorded Webinar:ARM Cortex SoC Prototyping Platform for Industrial Applications
White Paper:ARM Cortex SoC Prototyping Platform for Industrial Applications
Upcoming Events:SEE/MAPLD Presentation ‘Hybrid Platform for High Capacity FPGA Validation and Verification’