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Aldec to offer ‘DAC CHAT’ Technical Sessions Live Online

Date: Jun 23, 2014Type: Release

Henderson, NV – June 23, 2014 – Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for FPGA and ASIC devices, is offering the most popular ‘DAC Chat’ Technical Sessions from this year’s Design Automation Conference online.  

Register for live webinar events online at www.aldec.com/events.

OSVVM: Advanced Verification for VHDL with Synthworks    
Date: Thursday, June 26, 2014
Register for EU 3:00 PM - 4:00 PM CEST
Register for US 11:00 AM - 12:00 PM PDT

OSVVM provides functional coverage and randomization utilities that layer on top of transaction level modeling based VHDL testbench to create either basic Constrained Random tests or more advanced Intelligent Coverage based Random tests.  This simplified approach allows utilization of advanced randomization techniques, which can also be easily mixed with directed, algorithmic, and file-based test generation techniques.

Requirements-Based Verification for
Safety-Critical FPGAs
Date: Thursday, July 31, 2014
Register for EU 3:00 PM - 4:00 PM CEST
Register for US 11:00 AM - 12:00 PM PDT

 

Requirements are the basis of the verification activities for safety-critical FPGAs. Safety-critical industry standards for avionics, industrial and automotive enforce a requirements-based verification process to ensure safe and reliable FPGAs. Learn in this webinar the associated challenges to requirements management and verification management for safety-critical FPGAs and uncover a solution for requirements management, traceability, impact analysis, test plan management and verification management.

Prototyping Over 100 Million Gates
Date: Thursday, August 7, 2014
Register for EU 3:00 PM - 4:00 PM CEST
Register for US 11:00 AM - 12:00 PM PDT

 

As today's SoC and ASIC designs evolve to integrate the latest embedded processors, media interfaces, and high-speed serial communication, FPGA prototyping platforms are struggling to maintain the pace of designs surpassing the 100 million ASIC gate count. With the evolution of modular architectures and robust scalable backplanes, FPGA prototyping vendor solutions such as Aldec HES-7™ are able to keep pace with hardware designers.

SoC Emulation Made Easy
Date: Thursday, September 11, 2014
Register for EU 3:00 PM - 4:00 PM CEST
Register for US 11:00 AM - 12:00 PM PDT

 

Early access to the emulation platform allows HW/SW teams to work concurrently, enabling HW/SW co-design and co-verification. This webinar outlines a solution that allows using FPGA boards in different modes; simulation acceleration, transaction-level emulation or integrated with virtual platforms. Another option is in-circuit emulation with speed adapters that provide a high-speed hardware interface. 

Quick Introduction to SCE-MI
Date: Thursday, September 18, 2014
Register for EU 3:00 PM - 4:00 PM CEST
Register for US 11:00 AM - 12:00 PM PDT

 

Standard Co-Emulation Modeling Interface (SCE-MI) is Accellera's standard for bridging two realms: untimed (HVL, testbench on host) and timed (HDL, design in emulator). SCE-MI offers the flexibility to choose an emulation platform and become vendor independent, critical today when advanced FPGA technology allows for building fast and large capacity emulators at a fraction of the cost.

Design Rule Checks in FPGA Design
Date: Thursday, September 25, 2014
Register for EU 3:00 PM - 4:00 PM CEST
Register for US 11:00 AM - 12:00 PM PDT

 

Design Rule Checks have traditionally been associated with large ASIC designs and have been used effectively to catch static violations as early as possible, hereby reducing debug time in the subsequent verification process. The benefits are the same when using DRC in the design methodology of FPGA. This webinar outlines a solution that offers advanced check for structural CDC issues, extensive coverage of industry standard design rules, and addresses issues early in the design cycle.

About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com

 


Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are the property of their respective owners.

Media Contact: Aldec, Inc.                               
Christina Toole, Corporate Marketing Manager
+ (702) 990-4400
christinat@aldec.com
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