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Aldec to offer DAC Technical Sessions Live Online

Date: Jul 6, 2015Type: Release

image_dac_2015Henderson, NV – July 6, 2015 – Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for FPGA and ASIC devices, is offering our most popular DAC Technical Sessions from this year’s Design Automation Conference online.  

Register for live webinar events online at www.aldec.com/events.

 

 

 


FPGAs for Verification, UVM Simulation Acceleration with Scalable FPGA Platforms
Recorded Webinar

In this webinar we will introduce an approach where UVM tests can be accelerated with the use of an FPGA co-emulator.  The approach is built upon industry standards SystemVerilog and SCE-MI, and requires no changes to the test environment to accelerate.  This enables tests to be moved seamlessly from simulation to the accelerator and back again


Go with the flow (Python)
Recorded Webinar

By tightly coupling the hardware and software elements into an engineered flow, a rapid and agile approach to FPGA development becomes possible. Taking the best of open and closed source tools, Potential Ventures has created a flow that stands up to the rigorous demands of the cutting edge financial services sector where project times are measured in days and weeks rather than months and years.  The webinar will cover all aspects of RTL development including verification, regressions, co-simulation of hardware and software, interactive debug tools, documentation, metric tracking and more.


Eliminating Clock Domain Crossing (CDC) Issues Early in the Design Cycle
Date: Thursday, August 13, 2015
Register for EU 3:00 PM - 4:00 PM CEST
Register for US 11:00 AM - 12:00 PM PDT

In this webinar, we’ll discuss typical synchronizer structures to put in place for CDC crossings as well as the most common mistakes in their structure. We’ll also cover some of the functional problems that often arise due to incorrect synchronization, as well as how to verify a project against CDC issues during the RTL design and RTL simulation design stages.


OSVVM for VHDL Testbenches
View Recorded Webinar and Slides

In 2015, Open Source VHDL Verification Methodology (OSVVM) added comprehensive error and message reporting (January, 2015.01) and memory modeling (June, 2015.06). With this expanded capability, this presentation takes a look at the big picture methodology progressing transactions to randomization to functional coverage to intelligent coverage to alerts (error reporting) and logs (message reporting) to memory modeling.



About Aldec
Aldec, Inc., established in 1984 and headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware Emulation, Hardware Acceleration, FPGA Prototyping Systems, Design Rule Checking, CDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification, and Military/Aerospace solutions. www.aldec.com

 


Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are the property of their respective owners.

Media Contact: Aldec, Inc.                               
Christina Toole, Corporate Marketing Manager
+ (702) 990-4400
christinat@aldec.com
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