Company Overview

Aldec, Inc. is an industry-leading Electronic Design Automation (EDA) company delivering innovative design creation, simulation and verification solutions to assist in the development of complex FPGA, ASIC, SoC and embedded system designs. View Product Line (pdf)

With an active user community of over 35,000, 50+ global partners, offices worldwide and a global sales distribution network in over 43 countries, the company has established itself as a proven leader within the verification design community.



Aldec market share is estimated at 38% of all mixed-language RTL Simulators sold to FPGA designers worldwide. (Excludes OEM simulators supplied directly from FPGA vendors).

Aldec delivers high quality EDA solutions for government, military, aerospace, telecommunications, automotive and safety critical applications. Large companies including IBM, GE, Qualcomm, Rohde and Schwarz, Bosch, Texas Instruments, Applied Micro, Hewlett Packard, Toshiba, Intel, NEC, Mitsubishi, LG, Hitachi, NASA, Invensys, Westinghouse, Raytheon, Panasonic, Lockheed Martin, Samsung, as well as mid-size and small firms utilize Aldec EDA verification suites to boost product performance, cut design development cycles and reduce cost.

Technology Patents

  • US Patent#4,791,357: Electronic circuit board testing system and method
  • US Patent#4,827,427: Instantaneous incremental compiler for producing logic circuit
  • US Patent#5,479,355: System and method for closed loop operation of schematic designs with electrical hardware
  • US Patent#5,051,938: Simulation of selected logic circuit designs
  • US Patent#6,578,133: MIMD Array of Single Bit Processors for Processing Logic Equations in Strict Sequential Order
  • US Patent#6,915,410: Compiler synchronized multi-processor programmable logic device with direct transfer of computation results among processor 


  • Adds SystemVerilog DRC to ALINT-PRO
  • FPGA-based Accelerator for High Frequency Trading platforms
  • HW/SW Co-Simulation and Co-Debugging of Xilinx Zynq PS and PL
  • Introduces Finite Statement Machine Coverage for Safety-Critical FPGAs
  • Multi-FPGA Partitioning for ASIC Prototyping in HES-DVM
  • Releases ADAS embedded solution
  • Adds largest Xilinx® Ultrascale™ to HES Emulation/Prototyping platform
  • Releases TySOM Product Line based on Xilinx® Zynq™ main boards and FMC daughter cards
  • Pre-Silicon Verification Spectrum for digital ASIC designs
  • Introduces Hybrid Co-Emulation with ARM® Fast Models
  • Delivers 50+ successful DO-254 projects supported by CTS physical test systems
  • Releases ALINT-PRO with CDC Verification
  • Largest FPGA-based prototyping system at 288M ASIC gates
  • Celebrates 30 years in EDA
  • Releases Active-HDL 10.1 with 64-bit simulation support
  • Elbit Systems deploys Aldec DO-254/CTS
  • Delivers Visual Mapping Solution for UVM Verification Environments
  • Solves DO-254 challenge by adding Requirements Reviewer to Spec-TRACER™
  • Supports UVM 1.2 Library
  • Distributes NEC CyberWorkBench® high level synthesis solution
  • Releases Spec-TRACER™ Requirements Lifecycle Management
  • Launches Fast Track online training
  • Hitachi deploys ALINT™ on next-gen FPGA design
  • Enters SoC/ASIC Prototyping Market with HES-7
  • Best FPGA Design & Verification Platform Provider, China
  • Releases Aldec Cloud
  • Launches DO-254 Training Program
  • Jointly launches OSVVM, VHDL Verification
  • Opens Office in the UK Supporting Europe
  • Avnet Asia Pacific Distributes Aldec FPGA Simulator
  • UVM 1.0, OVM 2.1.2 & VMM 1.1.1a Support
  • Mirror-Box™ Debugging Technology
  • Releases 4 MHz Design Emulator
  • Best FPGA Design & Verification Platform Provider, China
  • Altium Embeds Aldec Simulator in Altium Designer
  • Active-HDL: Best FPGA Design & Simulation Tool in China
  • Opens Offices in Taiwan and Israel
  • Releases Support for VHDL IEEE 1076-2008
  • Avnet Japan Distributes Aldec FPGA Simulator
  • Releases DO-254 Design Rule Library for ALINT
  • Opens Office in India
  • Releases ALINT™: Design Rule Checker (STARC – Japanese Consortium of 11 ASIC Companies)
  • Opens Office in Japan
  • Released DO254-CTS (Compliance Test System)
  • Signed Strategic OEM agreement with Lattice® Semiconductor Nasdaq: LSCC
  • Released Actel Prototyping Solution – RTAX-S Antifuse to Flash device
  • EETIMES Ranked Aldec no. 3 in FPGA User Survey (behind Synplicity and Altera)
  • Opens Offices in Beijing and Shanghai, China
  • Awarded Patent ClockConversion™ (ASIC Clocks to FPGA Technology Conversion)
  • Released Optimized Verilog Simulator, based on support 32 and 64-bit Simulation Technology
  • Released SystemVerilog and SystemC System Level Design Tools
  • Released HES™ Hardware Emulation, Acceleration and Prototyping Solutions
  • Released Riviera-PRO™: Common Kernel, Multi-platform Mixed HDL Software Simulator
  • Named 2002 Southern Nevada Distinguished Business of the Year, Nevada Economic Commission
  • Signed Strategic OEM agreement with Synplicity® Nasdaq: SYNP
  • Signed Strategic OEM agreement with Cypress® NYSE: CY
  • Released Active-HDL™: Graphical Design Entry and Mixed Language Simulator
  • Signed Strategic OEM agreement with Xilinx® Nasdaq: XLNX
  • Released Active-CAD™ Releases Active-CAD™ - a Windows Based Schematic & Gate Level Simulator
  • Releases SUSIE™ (Standard Universal Simulator for Improved Engineering), DOS Simulator
  •  Company is Established
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