Aldec Releases Active-HDL 10.1 with 64-bit simulation support
Henderson, NV – December 8, 2014 – Aldec, Inc., announces the latest release of its mixed-language, FPGA design platform, Active-HDL™ 10.1. Popular with designers for more than 15 years for FPGA design entry and simulation due to its award-winning and intuitive GUI and high performance simulator, Active-HDL now offers support for 64-bit simulation to meet the growing demand of simulation of larger designs.
“The development of larger and more complex FPGA devices has increased the popularity of 64-bit CPU architectures that support higher RAM capacity.” said Satyam Jani, Active-HDL Product Manager. “Customers can now leverage Active-HDL, with support for 64-bit simulation, on their more powerful machines.”
Active-HDL is an HDL-based FPGA Design and Simulation solution that supports the newest FPGA devices available from all leading FPGA vendors. The high-performance, mixed-language solution interfaces with nearly one hundred twenty (120) third party vendor tools and provides FPGA designers a single platform that can be used independently of the targeted FPGA design flow. Active-HDL 10.1 supports design creation and simulation of the newest industry-leading FPGA devices from Altera®, Lattice®, Microsemi™ (Actel), Quicklogic® and Xilinx®.
The latest release of Active-HDL also includes numerous new features, enhancements, and performance optimizations. For additional information, tutorials, free evaluation download and What’s New Presentation, visit www.aldec.com/Products/Active-HDL.
Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com
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|Media Contact:||Aldec, Inc.
Christina Toole, Corporate Marketing Manager
+ (702) 990-4400