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Q3-2011 - Aldec™ Design and Verification Newsletter

Date: Jul 21, 2011Type: Newsletter

Free Assertions Training Seminars

Assertions for HDL Designers

Thursday, August 18, 2011, 9:00am — 1:00pm
The Biltmore Hotel, Santa Clara, CA
Email us if you’d like to see Aldec Seminars in your town next!

Join us for a free, half-day seminar created for hardware designers with practical knowledge of Verilog and/or VHDL. This class is designed to prepare the student for practical usage of assertions in verification tools by explaining basic ideas, introducing key elements of assertions illustrated with simple examples and presenting complete design demonstrating various uses of assertions. Examples will use SystemVerilog Assertions (SVA) and Property Specification Language (PSL) in parallel, giving students more options of further study. Presenter: Jerry Kaczynski, Aldec Research Engineer.


UVM Transaction-Level Visual Debugging 

Aldec has expanded support for the Universal Verification Methodology (UVM) with comprehensive transaction-level visual debugging. The new capabilities for transactions recording and visualization enable engineers to utilize Riviera-PRO 2011.06 advanced debugging infrastructure without having to manage basic mechanisms for transactions handling. The new UVM 1.0 transaction-level debugging capabilities are immediately available with the latest release of Riviera-PRO 2011.06 at no cost to customers with a valid maintenance contract and SystemVerilog verification support.


Technology

SystemVerilog: Who? What? When? Where?

SystemVerilog was released as a complete standard in 2009 and will stay with the digital design community whether we like it or not. Quite surprisingly, the only group of people that welcomed SV enthusiastically was the Verification Engineer Guild. Other groups still seem to treat SV with reserve, partially justified by unbearably wide scope of the new language. This presentation explains which areas of SystemVerilog should be implemented by hardware designers. Main topics include Design Subset, Assertions, Verification Subset, Verification Methodologies (OVM/UVM).
Play Webinar

Cloud-based Verification: Examine the Possibility

The advancement of cloud computing is a key development in the latest time and EDA industry is no exception in this domain. Many EDA vendors have been providing different services via clouds but these services are mainly for trying out software or testing the software. At this point there are obvious concerns about security and licensing models. Also the network bandwidth may seem to be the issue for interactive EDA tools. Examine the possibility to use clouds as a technology to manage your verification and simulation using Aldec’s ecosystem.

In-Target Testing for Xilinx® Devices for Level A/B DO-254 Compliance

Functional verification of the design in real hardware has been a serious undertaking when designing for DO-254 compliance. Designers are presented with significant challenges in meeting chapter 6.2 Verification Process of DO-254 such as requirements traceability, limited controllability/visibility of FPGA I/Os, development of test vectors to match RTL simulation, creation of multiple testing environment for sets of test cases, running the design in the target device “at speed”, and lack of automation in the verification cycle, which all of them ultimately results to a time consuming verification process.

Aldec’s DO-254/CTS™ is a certifiable “at-speed” and “in-target” testing environment for complex designs residing in Xilinx devices, and is dedicated to address the true specification of DO-254 via FAA AC 20-152 that complex devices such as FPGAs and PLDs must be tested and verified to requirements at the device level. DO-254/CTS™ consists of a COTS mother board, custom daughter board and proprietary software package designed to provide a single environment to test all FPGA level requirements ideal for Level A/B DO-254 certification.


 

Aldec is Tweeting!

Did you know you can get the latest updates from Aldec on Twitter? Simply follow Aldec on Twitter at twitter.com/#!/aldecinc Inc and we will keep you up-to-date on Aldec news and promotions. Click here to follow Aldec on Twitter.


Product updates


Riviera-PRO™ 2011.06
This release includes the latest versions of industry-standard verification libraries (UVM 1.0, OVM 2.1.2, and VMM 1.1), advanced transaction-level debugging tools, more robust support for the latest SystemVerilog language standard (IEEE 1800-2009), preliminary support for unified coverage database (based on Accellera’s Unified Coverage Interoperability Standard), and new productivity tools in the graphical interface.

DVM™ 2011.04
The new release of Design Verification Manager software, DVM™ 2011.04, supports SCE-MI standard and provides 4 MHz emulation speed for designs with 10 million ASIC gates. The new version of DVM automates the entire design setup process including the insertion of SCE-MI transactors into the user’s design and SCE-MI API functions to interface with the C/C++ model or testbench on the software side. Significant improvements in dynamic debugging have also been implemented to provide full visibility into the design, visualization of results in a waveform viewer, setup of hardware breakpoints and triggers, and memory viewer/editor.


UVM Transaction-Level Visual Debugging 

Aldec has expanded support for the Universal Verification Methodology (UVM) with comprehensive transaction-level visual debugging. The new capabilities for transactions recording and visualization enable engineers to utilize Riviera-PRO 2011.06 advanced debugging infrastructure without having to manage basic mechanisms for transactions handling. The new UVM 1.0 transaction-level debugging capabilities are immediately available with the latest release of Riviera-PRO 2011.06 at no cost to customers with a valid maintenance contract and SystemVerilog verification support.


UVM Transaction-Level Visual Debugging 

Aldec has expanded support for the Universal Verification Methodology (UVM) with comprehensive transaction-level visual debugging. The new capabilities for transactions recording and visualization enable engineers to utilize Riviera-PRO 2011.06 advanced debugging infrastructure without having to manage basic mechanisms for transactions handling. The new UVM 1.0 transaction-level debugging capabilities are immediately available with the latest release of Riviera-PRO 2011.06 at no cost to customers with a valid maintenance contract and SystemVerilog verification support.


Riviera-PROHW/SW Co-VerificationVirtual Modeling

Products

Riviera-PRO™ 2011.6

  • Advanced Verification Platform
    (OVM/UVM, VMM)
  • High-Performance Simulator
  • Assertion-Based Verification
  • Code and Functional Coverage
  • Transaction-Level Debugging
  • DSP Co-Simulation with
    MATLAB®
  • Now with 64-bit Windows® & Linux Simulation

Active-HDL™ 8.3 sp1

  • FPGA Design & Verification
  • Mixed-Language Simulator
  • Assertions
  • Coverage Tools
  • PCB Interface
  • Documentation Tools

ALINT™ 2010.10 sp1

  • Early Bugs Detection
  • Phase-Based Linting Methodology
  • Over 400 Design Rules
  • VHDL, Verilog®, & Mixed
  • User-defined Rules
  • Integrated Debugging Environment

HES-DVM™ 2011.10

  • 4MHz Emulation Speed,
    37 Million ASIC Gates
  • SystemVerilog
  • 100% Visibility for Dynamic
    Debugging
  • Guided Partitioning
    Visualization
  • Integration with Riviera-PRO Post Simulation Debug
  • 6 Virtex-6™ Board Support (DINI Group DN2076K10™) 

About Aldec

Headquartered in Henderson, Nevada, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions.

 

Did You Know?


• Aldec is working to provide a gateway to Active-HDL users who wish to take advantage of 64-bit Linux simulation.
This will enable those users who want to utilize 64-bit architecture for those large and memory-hungry designs that require more than 4 GB of RAM.


• ALDEC has a leading level of support for the latest release of VHDL standard (VHDL 2008). Most recent additions include unconstrained array elements in array and record types, generic types and subprograms in packages. Remember to update your simulators to the latest version to get access to all those exciting features.


• Riviera-PRO allows you to jump from an event on a signal shown in the Waveform Viewer to the statement that caused that event!
To enable the Show Event Source functionality, invoke the simulator using the -ses argument for the asim command. If you use the GUI to initialize simulation, make sure that the Enable show event source option is selected in the Simulation | Dataset category in the Preferences dialog box.

• Once a linting session is over, ALINT can display a synthesis report with detailed information about the recently analyzed design.
This information includes but is not limited to the number of equivalent logic gates, flip-flops, latches, and number of regular code vs. comment lines. 

 


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