Aldec Releases Active-HDL 9.1 Supporting Simulation of the Newest FPGA Devices
Henderson, NV – November 1, 2011 – Aldec, Inc. today announced the immediate availability of Active-HDL version 9.1, an award-winning HDL-based FPGA Design and Simulation solution that supports the newest FPGA devices available from all leading FPGA vendors. The high-performance, mixed-language solution interfaces with nearly one hundred (100) third party vendor tools and provides FPGA designers a single platform that can be used independently of the targeted FPGA design flow. Active-HDL 9.1 supports design creation and simulation of the newest industry-leading FPGA devices from Altera®, Atmel®, Lattice®, Microsemi™ (Actel), Tabula, Quicklogic® and Xilinx®.
Known to FPGA designers as a tool-of-choice for ease and convenience (with design creation, documentation, code coverage and simulation bundled into one product) the latest release of Active-HDL includes even more benefits, such as:
- Integration with Aldec Riviera-PRO™ verification products - providing a gateway to 64-bit simulation and SystemVerilog Verification;
- HDL Code Browser Tool for on-the-fly error detection prior to compilation;
- Unified Coverage Database – a new single source database to manage different types of coverage;
- Extended documentation support to assist in DO-254 compliance requirements;
- Enhanced support of VHDL-2008 and PSL/SVA Assertions;
- Time saving, new features within the HDL Editor; and
- Improvements to the Block Diagram Editor and Waveform Viewer
“This release of Active-HDL allows users to switch between Aldec products during different stages of design and verification,” said Satyam Jani, Aldec Software Division Product Manager. “The advanced verification interface allows users to move between products effortlessly and automatically generates scripts which can be used to run simulation on 64-bit machines using Aldec’s Riviera-PRO verification products.”
The enhanced level of automation that Active-HDL 9.1 brings within the design creation tools enables customers to save a significant amount of time and detect errors in the source code even before compilation with the new HDL code browser tool. The robust auto-complete technology build into the HDL Editor, language templates and phrase highlighting will enable design teams to quickly and efficiently develop, search and share their HDL code.
All customers with a current maintenance contract are eligible to receive the update at no cost. New customers and customers without current maintenance contracts are invited to contact their local Aldec Distributor to receive additional information on the latest release.
For additional information about Active-HDL 9.1 including tutorials, downloads and a What’s New presentation, please visit www.aldec.com/Products/Active-HDL.
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com
||Christina Toole, Marketing Manager