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Open-Source VHDL Verification Methodology (OS-VVM) User Group to unveil Advanced Test Methodologies for VHDL Designers at DAC

Date: May 31, 2012Type: Company

San Francisco – May 31, 2012  –  Aldec, Inc., earlier this year announced the availability of Open Source - VHDL Verification Methodology (OS-VVM™), delivering advanced verification test methodologies to VHDL design engineers. Once again underscoring its commitment to provide continued support to the VHDL design community, Aldec will host the OS-VVM community's first User Group Meeting at next week's Design Automation Conference (DAC 49).

 

Event: OS-VVM User Group Meeting
Date:  Monday, June 4th (DAC Free Monday)
Time:  2:00pm – 3:00pm
Location: DAC 49, Moscone Center, San Francisco
  Hosted by Aldec – Booth #2126

 

Presenters:

Jim Lewis, Synthworks (Creator of the original OS-VVM packages)
Jerry Kaczynski, Aldec Research Engineer

 

Agenda:

• OS-VVM Overview

• Discussion

o Current status and future development plans for OS-VVM
o OS-VVM User Forum and importance of community
o Future VHDL standard revisions

• Open Discussion/Questions

o  Jim Lewis, creator of original OS-VVM packages will be present and ready to answer your questions.

 

Unable to make the User-Group Meeting but want to learn more? Visit www.os-vvm.org to attend the OS-VVM Presentation: High-Level VHDL Verification Doing Well with Help of New OS-VVM Community at DAC at a more convenient time.

 

About OS-VVM

(OS-VVM) is an intelligent testbench methodology that allows mixing of “Intelligent Coverage” (coverage driven randomization) with directed, algorithmic, file based, and constrained random test approaches. The methodology can be adopted in part or in whole as needed. OSVVM allows users to add advanced verification methodologies current testbenches without having to learn a new language or discard existing testbench or testbench models. www.os-vvm.org

 

About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com


Aldec is a registered trademark of Aldec, Inc.  All other trademarks or registered trademarks are property of their respective owners.

Media Contact:

Christina Toole, Aldec, Inc.
+1 (702) 990-4400
christinat@aldec.com

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