Q4-2011 - Aldec™ Design and Verification Newsletter

Date: Oct 6, 2011Type: Newsletter

Aldec Honored for Superior FPGA Verification

Aldec has once again been honored by China's electronics information leader, Chinese Electronics News (CEN), this year with the Best FPGA Design & Verification Platform Provider Award for 2011. This prestigious award, recognizing top contributors in the semiconductor industry, was presented at the third annual FPGA Industry Development Forum in Xi'an, China.

The forum honored the following companies:
Best FPGA Design & Verification Platform Provider: Aldec, Inc.
Best FPGA Technology: Xilinx and Altera
Best Performance-Price Ratio FPGA Product: Microsemi SmartFusion

The Best FPGA Design & Verification Platform Provider award recognizes the robustness of Aldec’s design and verification platform, which has all the tools necessary for efficient development of today’s FPGA devices that have a complexity level comparable with traditional ASICs.

Get ahead with Training Seminars from Aldec

Increase your productivity and enhance your skills by attending an Aldec Training seminar. In today’s competitive atmosphere, the ability to adopt new technology quickly and reduce design time cycles is key. Aldec’s in-house trainers and training partners offer a number of excellent training opportunities. View upcoming Trainings at www.aldec.com/events.


DO-254 Seminar: Optimizing Requirements for Verification
Presenter: Randall Fulton, FAA Consultant DER
Date: Thursday, November 17, 2011, 8:00AM – 5:00PM
Location: The Mandalay Bay Hotel, Las Vegas, NV

Fee Seminar: Assertions for HDL Designers
Presenter: Jerry Kaczynski, Aldec Research Engineer
Dates: October 13, 2011 Irvine, CA 
            November 3, 2011 San Diego, CA


STARC RTL Design Style Guide Seminars
Dates: October 14, 2011 Osaka, Japan 
            October 27, 2011 Yokohama, Japan
            October 28, 2011 Yokohama, Japan

Designs have become increasingly complicated and often require collaborative work by a large number of designers. RTL Design Style Guide sets a style for RTL design and provides recommendations that can increase efficiency and benefit communication.

No Cost Workshops from Aldec Japan
October 20 & November 10: Improving Design Quality and Re-use Acceleration Workshop
October 19 & November 9: Simulation Acceleration Workshop
October 25 & November 25: Assertion (SVA) Workshop
October 26 & November 30: Active-HDL Workshop

Active-HDL Training - Xilinx Training Conference with Avnet
Dates: October 28, 2011
Location: Osaka, Japan


Struggling to Navigate Large HDL Files?

Is finding an instance declaration or component a tedious task? What if you are reviewing HDL file from another engineer and wish to quickly learn about the structure of their code? Wouldn’t it be nice if a tool could detect errors such as missing “;” at the end of the line well before compilation and even linting? Active-HDL 9.1 (available in November) will introduce a new tool called Code Browser to help engineers deal with large HDL files more efficiently.
Key Benefits:

  • Recognizes various items from the code such as architecture, ports, signals, instance declaration, functions, etc. and displays them in a convenient structure.
  • Structure view allows you to learn the code quickly and helps locate items directly without having to scroll.
  • On-the-fly error detection allows users to fix errors while writing code. Don’t wait for the compiler to detect errors that can easily be fixed while writing code.

Transaction Level Co-Emulation with Virtual Platforms

Virtual platforms play a significant role in system level development, but require integration with ultra-fast emulation systems for HW/SW co-verification. Aldec introduces the new integration of Aldec's Transaction Level Emulation System with Imperas' OVPsim virtual platform simulator. Hardware and software design teams are now able to implement virtual models of processors, memory and peripheral modules while the RTL modules run in the emulator board. This integration provides a high performance solution, ideal for early HW/SW co-development and architectural exploration.

Automated Code Reviews for Fail-Safe Designs

A review of HDL design best practice coding guidelines that should be considered for any safety-critical device, including aerospace designs. Automating code base analysis process is a critical requirement for fail-safe designs as it provides added benefit of documented, followed, and reviewed coding standards. Learn how to automate code analysis using the Phase-Based Linting (PBL) methodology, one of the two possible approaches to the design analysis and refinement process in ALINT. Traditional – all necessary coding guidelines (hundreds of design rules) are applied at once. This may result in thousands of error and warning messages from a single linting session. In addition, the order of violations analysis is unknown hence the traditional approach is not efficient because of the design issue interdependencies.

New RTAX Rad-Tolerant Prototyping Options Available

Aldec has recently added prototyping solutions for the RTAX4000s as well as both RTAX2000D & 4000D. Tis is in keeping with Aldec’s goal of offering a prototyping solution for all Microsemi radiation-tolerant anti-fuse FPGAs. All solutions offer RTAX footprint compatible prototyping boards. Optional netlist conversion software is also available. Hundreds of Aldec’s adapter boards have been shipped. This has allowed scores of companies in the space-flight systems design realm world-wide to save money and cut time to market. For more information, please visit aldec.com/products/RTAX.

Passionate about VHDL and its future?

Do you know that the majority of hardware description languages (including SystemVerilog) is developed by companies that purchased IEEE-SA membership and individual users have no say in the process?
VHDL does not follow this trend, and the working group developing the next version of the standard is looking for passionate individuals who would like to spend some time improving the language. Everyone is welcme and encouraged to visit www.eda.org and help make a decision.

Product updates

Riviera-PRO™ Available October 2011

The latest release of Riviera-PRO brings you a pack of new productivity features, support for new HDL Language constructs (VHDL and SystemVerilog), and incremental updates of the verification libraries shipped with the tool. The new Language Templates in the HDL Editor is just one of the new productivity features that come in handy while working with the source code. And, as every new release, Riviera-PRO 2011.10 keeps up with the latest verification libraries and includes all of the industry-standards (UVM 1.1, OVM 2.1.2, and VMM 1.1) as a part of default installation.

Active-HDL™ Available November 2011

The upcoming release of Active-HDL 9.1 includes many new features and numerous enhancements to simplify team-based designing and to increase productivity. Along with our main focus of providing robust support for latest language standard such as VHDL-2008 and SystemVerilog 2009 design. Additional features include:

  • New Code Browser tool for better navigation inside HDL code and on-the-fly error detection before compilation.
  • Direct interface to Aldec Linux solutions to allow users to move between products and platforms more easily.
  • Unified Coverage Interoperability Standard (UCIS) compatible coverage database – Preview.
  • Numerous enhancements in HDL Editor – Phrase highlighting, Auto-complete signal name, Zooming functionality.

ALINT™ Available December 2011

The new release of ALINT brings valuable tools for efficient project collaboration and information sharing across your organization. These new tools include:

  • Interactive HTML Reporting that enables efficient design analysis even without the tool installed.
  • Custm Policy Files Annotation that enables arbitrary comments to be associated with every rule included.
  • Exclusion Files Annotation, the essential tool for project documentation that enables justifying every waiver introduced.

The new release also brings many improvements and exciting new features such as native support for 64-bit Windows, simplified SystemVerilog handling, and full project and library-level compatibility with Riviera-PRO 2011.10. In addition, we have implemented numerous productivity features based on requests coming from our customers – make sure to leverage all these benefits as soon as the new build is available!


Riviera-PRO™ 2011.10

  • Advanced Verification Platform (OVM/UVM, VMM)
  • High-Performance Simulator
  • Assertion-Based Verification
  • Code and Functional Coverage
  • Transaction-Level Debugging
  • DSP Co-Simulation with MATLAB®

Active-HDL™ 9.1

  • FPGA Design & Verification
  • Mixed-Language Simulator
  • Assertions
  • Coverage Tools
  • PCB Interface
  • Documentation Tools

ALINT™ 2011.10

  • Early Bugs Detection
  • Phase-Based Linting Methodology
  • Over 400 Design Rules
  • VHDL, Verilog®, & Mixed
  • User-defined Rules
  • Integrated Debugging Environment

HES-DVM™ 2011.10

  • 7MHz Emulation Speed, 37 Million ASIC Gates
  • SCE-MI 2.0 DPI-C Support
  • Integration with Riviera-PRO: Adding/Removing Debugging Signals and Emulation Start/Stop/Step
  • Dynamic Triggers - Flexible Probes

Did You Know?

Use virtual streams to display related transactions. In some cases, e.g. when relations are defined for transactions from different transaction streams, it may be convenient to view only those transactions that bear a particular relation. For that purpose, virtual transaction streams are provided. To create a virtual stream, expand relations for a transaction, right-click the selected relation button, and select Create Virtual Stream from the pop-up menu.


Script compatibility with other vendors. Riviera-PRO provides a Tcl converter for migrating existing ModelSim® and QuestaSim® macros to Riviera-PRO format. The converter substitutes ModelSim/QuestaSim commands and arguments with their Riviera-PRO counterparts. To use the converter, load the Aldec: MsimConverter package by using the Tcl package require command.


Preserve Signals in Active-HDL, by selecting an option called “Preserve signals when simulation is initialized”. This option maintains previously added signals in Waveform viewer when the simulation is reinitialized.




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