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HW/SW Co-Simulation for SoC FPGA designs
Aldec’s Co-Simulation Solution using QEMU and Riviera-PRO

Heterogeneous System on Chip (SoC) devices like the Xilinx Zynq 7000 and Zynq UltraScale+ MPSoC combine a high-performance processing system (PS) with state-of-the-art programmable logic (PL)....

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The Power of PCIe in Performance-based FPGA World
Understanding High speed serial data transfer

In today's world, when the entire computing industry is talking about high-performance and high-speed applications using FPGAs, just what are the factors that can assure such performance and speed?...

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Verification Effectiveness with Riviera-PRO: SystemVerilog Randomized Layered Testbench
Understanding SystemVerilog Layered Testbench

In this blog, I will discuss randomized layered testbenches used in SystemVerilog. We need to understand why we need it, ...

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Understanding the inner workings of UVM - Part 3
UVM Basics Part 3 of 3

In this blog, I am going to discuss different phases that UVM follows.   The reason why UVM came up with such phases is because synchronization among all design-testbench was necessary. Using Verilog and VHDL,...

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Understanding the inner workings of UVM - Part 2
UVM Basics Part 2 of 3

In this blog, my major focus is on explaining the concepts such as Sequence, Sequencer, Driver and showing how the communication takes place from sequence to sequencer and from sequencer to driver. In the previous blog, I included...

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Plots: A New Way To Analyze Data

Data analysis is often a very time consuming process for a hardware design or verification engineer. We always end up using the waveform viewer which may not be very efficient in giving us a high-level overview of what we’re looking for. Data that is spread across...

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Zynq-based Embedded Development Kit for University Programs
Cost-effective solution for HW/SW development projects

Creativity and innovation, which lead the society to success, rest on the foundational institutions such as schools and universities. They provide fertile soil to seed, grow and flourish enterprises....

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Understanding the inner workings of UVM
UVM Basics Part 1 of 3

We have all been witnesses to the rapid improvements of the iPhone processor chip every year. With the iPhone 8 featuring the newest A11 Bionic at 10 nm FinFET with 4.3 billion transistors, I can’t personally fathom the amount...

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Accelerating Simulation of Vivado Designs with HES
Improve verification speedup with Aldec’s HES-DVM

FPGA Design Verification Challenge The FPGA design and verification “ecosystem” changes rapidly to keep pace with the fast growing size of FPGA devices. The largest Xilinx Virtex UltraSCALE chips provide 4.4 Million logic cells...

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Software Driven Test of FPGA Prototype
Use development software to drive your DUT on an FPGA prototyping platform

Most everyone would agree how important FPGA prototyping is to test and validate an IP, sub-system, or a complete SoC design. Before the design is taped-out it can be validated at speeds near real operating conditions with physical peripherals and devices connected to it instead of simulation models. ...

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