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HW/SW Co-Simulation for SoC FPGA designs
Aldec’s Co-Simulation Solution using QEMU and Riviera-PRO

Heterogeneous System on Chip (SoC) devices like the Xilinx Zynq 7000 and Zynq UltraScale+ MPSoC combine a high-performance processing system (PS) with state-of-the-art programmable logic (PL)....

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The Race to Zero Latency for High Frequency Trading

The High-Frequency Trading (HFT) industry has received a lot of attention during the last few years. HFT is all about speed and minimizing latency: the faster you can run trading strategies and algorithms for analyzing minute price changes...

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FPGA vs GPU for Machine Learning Applications: Which one is better?
Can FPGAs beat GPUs?

FPGAs or GPUs, that is the question.   Since the popularity of using machine learning algorithms to extract and process the information from raw data, it has been a race between FPGA and GPU vendors to offer...

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How to develop an FPGA-based Embedded Vision application for ADAS, series of blogs – Part 1
FPGA “The winner for the low-power and high-performance vision-based applications”

When should we use the term “Vision for Everything”, as vision-based applications are entering various industries? It’s been a few years since the emergence of...

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Code Coverage in HDL Editor? Now That’s a Nice Feature.

For a long time I have been a fan of code coverage tools that are embedded into the simulators themselves, and which give you the ability to switch easily between the code and the coverage results. It is particularly helpful to have a way...

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VHDL-2017: Some of My Favorite Things

For the past several years I have had the privilege to chair the IEEE 1076 VHDL working group. In March we handed off the revisions to the VHDL LRM to our technical editor to finalize the document for balloting. As we are waiting for the standards process to finish up, I thought I would share my favorite new additions. Let me start with an executive summary: ...

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FPGA VHDL Verification
How can we do this faster and with better quality - at no extra cost?

This is actually possible – and with an average efficiency improvement of 20 to 50% for medium to high complexity FPGAs. Less for data path oriented designs and more for control or protocol oriented designs. At no extra cost....

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Beer, Cars, and Verification
My thoughts after DVCon Europe

As I write this, I am visiting the Aldec corporate office in the US on the day following their historical presidential election. It’s been a busy travel season for this product manager, and only a few weeks ago I was at DVCon Europe in Munich - the city of pork knuckles, beer... and of course, cars. ...

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It’s Time to Get Your University in Sync with Zynq
Insight From a College Student

It’s time for Universities to say goodbye to their outdated FPGA boards and introduce the Xilinx® Zynq™ chip. The Zynq chip is a device which combines an FPGA fabric with a processing unit. The Zynq chip is very similar to other FPGA devices, but ...

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Verifying Large FPGAs Isn't Easy
Guest Blog by Doug Perry, Senior Member Technical Staff at Doulos

The latest crop of FPGA devices are enormous when compared to ASICs that were built not that long ago. Verifying these ASICs required detailed plans, multiple tools, and sometimes special languages....

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