Introduction to Zynq™ Architecture

A brief examination of the Zynq processing system and its programmable logic

Farhad Fallahlalehzari, Application Engineer
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The History of System-on-Chip (SoC)

Do we prefer to have a small electronic device or a larger one? The answer will often be “the smaller one”. However, before the commercialization of small radios, many people were interested in having big radios for the extravagance. Subsequently, at the beginning of the emergence of compact radios, those who preferred the flamboyance of large radios refused using compact radios. Slowly, but surely, the overwhelming benefits of owning a more compact radio led to the proliferation of smaller devices. These days the progression of the technology enables cutting-edge companies to encapsulate different parts of a system into increasingly smaller devices, all the way down to a single chip, which added the System-on-Chip (SoC) concept to the electronics world. By way of an example of a SoC, I will explain the Zynq-7000 all-programmable SoC. It consists of two hard processors, programmable logic (PL), ADC blocks and many other features all in one silicon chip.

 

Before the invention of the Zynq, processors were coupled with a Field Programmable Gate Array (FPGA) which made communication between the Programmable Logic (PL) and Processing System (PS) complicated. The Zynq architecture, as the latest generation of Xilix’s all-programmable System-on-Chip (SoC) families, combines a dual-core ARM Cortex-A9 with a traditional (FPGA). The interface between the different elements within the Zynq architecture is based on the Advanced eXtensible Interface (AXI) standard, which provides for high bandwidth and low latency connections.

 

Before implementing the ARM processor inside the Zynq device, users were using a soft core processor such as Xilinx’s Microblaze. The main advantage of using Microblaze was, and remains, the flexibility of the processor instances within a design. On the other hand, the inclusion of hard processor in Zynq delivers significant performance improvements. Also, by simplifying the system to a single chip, the overall cost and physical size of the device are reduced.

 

Figure 1: Zynq overall view

Zynq Design Flow

The design flow for the Zynq architecture has some steps in common with a regular FPGA. The first stage is to define the specifications and requirements of the system. Next, during the system design stage, the different tasks (functions) are assigned to implementation in either PL or PS which is called task partitioning. This stage is important because the performance of the overall system will depend on tasks/functions being assigned for implementation in the most appropriate technology: hardware or software.

 

Next, the hardware and software development and testing should be done. Regarding the PL, the task is to identify the required functional blocks to achieve the design characteristics and also assemble them as IPs and make the appropriate connections between them. Likewise, the software activity is to develop code to run on the PS. Consequently, system integration and testing is required to wrap up the design. Fig. 2 shows the Zynq SoC design flow.

 

Figure 2: Zynq Design Flow Steps

Inside the Zynq

The PS and PL part of the Zynq are explained in this section.

 

Application Processing Unit (APU)

The APU contains two ARM cortex-A9 processor units each of which generally includes NEON unit, floating point unit (FPU), memory management unit (MMU) and L1 caches. In addition, the APU also consists of snoop control and L2 caches. Fig. 3, shows the structure of the APU.

 

• NEON: The Single Instruction Multiple Data (SIMD) is provided by this unit which brings major acceleration of DSP and media algorithms to the main ARM processor.
• FPU: This unit provides the acceleration for the floating point operations.
• Level 1 cache: Each processor has its own instruction and data caches for storing the instructions and data.
• MMU: It is responsible for translation of the virtual memory addresses to the physical memory addresses.
• Snoop control Unit (SCU): The interfacing task among processors, L1 and L2 caches is one of the main tasks of the SCU.
• L2 cache: It is shared between the two processors that enables them to access the newest update of a variable.

 

Figure 3: Application Processing Unit Structure

 

Programmable Logic Structure

Just like other FPGAs, the programmable logic portion of the Zynq SoC consists of configurable logic blocks (CLBs) which contains two slices. Each slice contains four look-up tables (LUTs), eight Flip-flops (FFs), and an accompanying switch matrix. Moreover, there are Block RAMs and DSP slices as well. Fig. 4, shows the structure of the PL.


• Slice: Each slice consists of resources to implement the combinatorial and sequential circuits.
• Look-up Table (LUT): To implement a logic function of up to six inputs, RAM, ROM or shift registers, the LUTs are used.
• Flip-flop (FF): For implementation of 1-bit register with reset functionality, this sequential element is used.
• Switch Matrix: It provides the connections among the different parts within and between the CLBs, as well as other parts of the PL.

 

Figure 4: Structure of the PL

 

The above may seem difficult if you are new to Zynq. But don’t worry, to make the process of learning very easy, Aldec TySOM EDK provides various tutorials for both beginners and more advanced users of Zynq. The EDK includes various references to help you get familiar with creating hardware and software projects for both standalone and Linux based applications. Moreover, there are some advanced tutorials for web servers, IoT gates with Amazon cloud, ADAS and etc. There is also a reference design which will teach you how to design a hardware and software project from the basic level to advanced one. Thus, no matter how familiar you are with Zynq devices, there is always something more to learn. Check out the list of TySOM tutorials here.

 

My favorite tutorials listed here are:

Creating a Hardware and Software Project to Blink LEDs TySOM -1-7Z030

Building and Configuring a Linux OS using the Yocto Project – TySOM-1-7Z030

Web Server Tutorial – TySOM-1-7Z030

TySOM IoT Gateway with Amazon Cloud Tutorial – TySOM-1-7Z030

TySOM-1-7Z030 Reference Design Part 1 and Part 2

 

The TySOM EDK has all the tools and hardware that you need to start the development. From Riviera-Pro advanced RTL simulator, to Vivado design suite and SDSoC to synthesize and accelerate the design. The TySOM embedded development boards come with all the peripherals you need for your projects. Aldec also provides various types of FMC HPC daughter boards for applications such as networking, ADAS, IoT, serial connectivity and etc. So, I do recommend you to check out Aldec’s TySOM boards, TySOM EDK and daughter boards for more info.

Farhad Fallahlalehzari works as an Application Engineer at Aldec focusing on Embedded System Design. He provides technical support to customers developing embedded systems. His background is in Electrical and Computer Engineering, concentrating on Embedded Systems and Digital Systems Design. He received his Masters of Science in Electrical Engineering from the University of Nevada, Las Vegas in 2016. He completed his Bachelors of Science in Electrical Engineering at Azad University, Karaj Branch, Iran in 2013.

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