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Accelerating Simulation of Vivado Designs with HES
Improve verification speedup with Aldec’s HES-DVM

FPGA Design Verification Challenge The FPGA design and verification “ecosystem” changes rapidly to keep pace with the fast growing size of FPGA devices. The largest Xilinx Virtex UltraSCALE chips provide 4.4 Million logic cells...

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Aldec Verification Tools Implement the ASIC Verification Flow
Insights from Dr. Stanley Hyduke, Aldec Founder and CEO

Aldec has, over the last 30 years, established itself as the preferred provider of high-performance, cost-effective verification tools for use in proving out complex FPGA designs. As the logic capacity and capability...

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Acceleration-Ready UVM
Guest Blog by Doulos CTO, John Aynsley

We hear that emulation is one of the fastest-growing segments in EDA right now, yet simulation still continues to be the main workhorse for functional verification, and SystemVerilog and UVM are everywhere you look....

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Reprogrammable, reprogrammable, reprogrammable: What’s great about FPGAs!
Guest Blog by Alex Grove, Applications Specialist at FirstEDA

I like FPGAs. My first experience with an FPGA was my university final year project where I demonstrated BIST with four Xilinx© 3000 devices; this was before FPGAs had JTAG built in. Filling up these devices...

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What inspired you to become an engineer?
National Engineering Week is February 22-28

This week, February 22-28, we celebrate National Engineers Week in the US to recognize the contributions to society that engineers make. During this time, there is added emphasis in schools on the importance of learning...

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Scaling the “Internet of Things”
With Aldec HES-DVM™

Happy New Year! January brought an unseasonably warm wave of weather to Las Vegas as International CES converged on the city this month. The size and scope of this worldwide consumer electronics tradeshow...

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How HES™ Technology Solved Problems for These Users
Verification and validation environment for SoC/ASIC designs

Recognizing a problem that engineers are facing and developing a solution has been Aldec’s rather straight-forward mantra for going on thirty years now. Aldec launched its Hardware Emulation Solutions (HES) product in 2003,...

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HES-DVM™ 2013.11 Delivers Increased Speed and Debugging
Introducing Turbo Mode and HesDebugApi

Aldec recently released HES-DVM 2013.11 which introduces an array of customer-requested new features and improved debugging capabilities, speed, and co-emulation infrastructure....

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Leverage Hardware Acceleration for Faster Simulation
Breaking the Bottleneck of RTL Simulation

Utilizing hardware acceleration in a System-on-Chip verification cycle can speed-up HDL simulation runs from 10-100x, while providing the robust debugging available from an RTL simulator....

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Aldec and Xilinx, Partnered for Success
HW/SW Emulation and Functional Verification of Xilinx FPGAs

As an Aldec Hardware Product Manager, I make the quick flight from our home base in Las Vegas to San Jose pretty regularly. This week, I’ll be joining Aldec Software Product Manager, Dmitry Melnik, as we head out to attend...

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