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Partition your Design for FPGA Prototyping
Easily create partitions with HES-DVM

Modern ASIC and SoC designs have increased in complexity such that multiple FPGAs of the largest capacity are now required to prototype the entire functionality of the design. As design sizes increase, more and more...

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Understanding the inner workings of UVM
UVM Basics Part 1 of 3

We have all been witnesses to the rapid improvements of the iPhone processor chip every year. With the iPhone 8 featuring the newest A11 Bionic at 10 nm FinFET with 4.3 billion transistors, I can’t personally fathom the amount...

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Don’t be a Slave to the Documentation

Are you a requirements engineer but your main goal is to provide well organized documentation? Do you have a great knowledge about the industry, business analysis and systems but you are struggling with the shape and look of your documentation?...

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Austin's Best Vegetarian Restaurants: The Quest Continues

If you’re headed to DAC, you should know it's fixing to be the hottest summer ever in Austin, but for brave and hungry meatless eaters, this town is an increasingly cool destination, with creative restauranteurs finding new ways to transform meaty favorites into plant-based edible delights....

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FPGAs in an SoC World
How modern FPGA architecture influences verification methodologies

The SoC domination observed so far in the ASIC industry is coming to the FPGA world and changing the way FPGAs are used and FPGA projects are verified. The latest SoC FPGA devices  ...

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Software Driven Test of FPGA Prototype
Use development software to drive your DUT on an FPGA prototyping platform

Most everyone would agree how important FPGA prototyping is to test and validate an IP, sub-system, or a complete SoC design. Before the design is taped-out it can be validated at speeds near real operating conditions with physical peripherals and devices connected to it instead of simulation models. ...

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Aldec Verification Tools Implement the ASIC Verification Flow
Insights from Dr. Stanley Hyduke, Aldec Founder and CEO

Aldec has, over the last 30 years, established itself as the preferred provider of high-performance, cost-effective verification tools for use in proving out complex FPGA designs. As the logic capacity and capability...

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Vegetarian Dining in Austin - DAC 2016
Helpful Tips From a Local

I moved to Austin a little over a year ago, and have quickly learned that this city is a progressive blue island in a sea of red. That's the conventional wisdom, and most of the time it holds up....

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Reprogrammable, reprogrammable, reprogrammable: What’s great about FPGAs!
Guest Blog by Alex Grove, Applications Specialist at FirstEDA

I like FPGAs. My first experience with an FPGA was my university final year project where I demonstrated BIST with four Xilinx© 3000 devices; this was before FPGAs had JTAG built in. Filling up these devices...

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Code Coverage – Can we get a little help here?
Productivity boost from Condition and Path Coverage

Don’t get me wrong, coverage analysis has been used by engineers for years now and it usefulness in improving productivity and verification environment quality can’t be stressed enough....

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