Aldec Design and Verification Blog Trending Articles Evaluating NVMe SSD Multi-Gigabit Performance using Aldec TySOM-3/3A Boards When is robustness verification for DO-254 projects complete? How to develop high-performance deep neural network object detection/recognition applications for FPGA-based edge devices HW/SW Co-Verification Environment for Hybrid Systems Using QEMU 35-years-old, and still on point No Risk No Fun What is Bird’s Eye View ADAS Application and How to Develop This Using Zynq® UltraScale+™ MPSoC FPGA? All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications 35-years-old, and still on point At this year’s Design Automation Conference, held on June 3, 4 and 5 in Las Vegas and about 10 miles away from our head office in Las Vegas, Nevada, we celebrated our 35th anniversary with a resounding reaffirmation of our raison d’etre: the provision of verification solutions for some of industry’s most pressing challenges.... Tags:ARM,ASIC,HES,SoC Like(3) Comments (0) Read more The Power of PCIe in Performance-based FPGA World Understanding High speed serial data transfer In today's world, when the entire computing industry is talking about high-performance and high-speed applications using FPGAs, just what are the factors that can assure such performance and speed?... Tags:Aceleration,ASIC,Co-simulation,Documentation,Embedded,Emulation,FPGA,FPGA Simulation,Hardware,HDL,IP,Prototyping,Simulation,SoC,Validation,Verification,Xilinx Like(2) Comments (0) Read more Problems Accessing Registers? – See how UVM RAL can help. As a digital design or verification engineer you know that certain features or configurations of the device can be achieved by programming some registers to set values. For example, a 32-bit register can have several fields within it... Tags:ASIC,Debugging,FPGA,Simulation,SystemVerilog,UVM,Verification Like(1) Comments (0) Read more Verification Effectiveness with Riviera-PRO: SystemVerilog Randomized Layered Testbench Understanding SystemVerilog Layered Testbench In this blog, I will discuss randomized layered testbenches used in SystemVerilog. We need to understand why we need it, ... Tags:Riviera-PRO,ASIC,Assertions,Co-simulation,Coverage,Debugging,Design,Documentation,FPGA,HDL,IEEE,OS-VVM,Randomization,Simulation,standards,SystemVerilog,UVM,Verification,Verilog Like(3) Comments (0) Read more Understanding the inner workings of UVM - Part 3 UVM Basics Part 3 of 3 In this blog, I am going to discuss different phases that UVM follows. The reason why UVM came up with such phases is because synchronization among all design-testbench was necessary. Using Verilog and VHDL,... Tags:ASIC,Co-simulation,Coverage,Debugging,Documentation,FPGA,OS-VVM,UVM,Verification Like(1) Comments (3) Read more Understanding the inner workings of UVM - Part 2 UVM Basics Part 2 of 3 In this blog, my major focus is on explaining the concepts such as Sequence, Sequencer, Driver and showing how the communication takes place from sequence to sequencer and from sequencer to driver. In the previous blog, I included... Tags:ASIC,Co-simulation,Coverage,Debugging,Documentation,FPGA,OS-VVM,UVM,Verification Like(2) Comments (0) Read more Partition your Design for FPGA Prototyping Easily create partitions with HES-DVM Modern ASIC and SoC designs have increased in complexity such that multiple FPGAs of the largest capacity are now required to prototype the entire functionality of the design. As design sizes increase, more and more... Tags:ASIC,FPGA,Prototyping,SoC Like(0) Comments (0) Read more Understanding the inner workings of UVM UVM Basics Part 1 of 3 We have all been witnesses to the rapid improvements of the iPhone processor chip every year. With the iPhone 8 featuring the newest A11 Bionic at 10 nm FinFET with 4.3 billion transistors, I can’t personally fathom the amount... Tags:ASIC,Co-simulation,Coverage,Debugging,Documentation,FPGA,OS-VVM,UVM,Verification Like(2) Comments (0) Read more Don’t be a Slave to the Documentation Are you a requirements engineer but your main goal is to provide well organized documentation? Do you have a great knowledge about the industry, business analysis and systems but you are struggling with the shape and look of your documentation?... Tags:ASIC,Documentation,FPGA Like(0) Comments (0) Read more Austin's Best Vegetarian Restaurants: The Quest Continues If you’re headed to DAC, you should know it's fixing to be the hottest summer ever in Austin, but for brave and hungry meatless eaters, this town is an increasingly cool destination, with creative restauranteurs finding new ways to transform meaty favorites into plant-based edible delights.... Tags:ASIC,Emulation,Verification Like(0) Comments (0) Read more
