Aldec Design and Verification Blog

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Linting RISC-V designs with ALINT-PRO

As the open-source RISC-V instruction set architecture (ISA) continues to gain momentum, the growing number of RISC-V design solutions, and their flexibility, creates a problem when choosing the most reliable and robust solution from a number of contenders....

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Connecting Emulated Design to External PCI Express Device

These days verification teams no longer question whether hardware assisted verification should be used in their projects. Rather, they ask at which stage they should start using it.   Contemporary System-on-Chip (SoC) designs are already sufficiently complex to make HDL simulation...

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ARM-based SoC Co-Emulation using Zynq Boards
Ready-to-use Co-Emulation Platform

Have you ever worked on a group project where you had to combine your work with that of a colleague of a different engineering discipline but the absence of an efficient means of doing so affected the project’s overall outcome?...

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35-years-old, and still on point

At this year’s Design Automation Conference, held on June 3, 4 and 5 in Las Vegas and about 10 miles away from our head office in Las Vegas, Nevada, we celebrated our 35th anniversary with a resounding reaffirmation of our raison d’etre: the provision of verification solutions for some of industry’s most pressing challenges....

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The Power of PCIe in Performance-based FPGA World
Understanding High speed serial data transfer

In today's world, when the entire computing industry is talking about high-performance and high-speed applications using FPGAs, just what are the factors that can assure such performance and speed?...

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Problems Accessing Registers? – See how UVM RAL can help.

As a digital design or verification engineer you know that certain features or configurations of the device can be achieved by programming some registers to set values. For example, a 32-bit register can have several fields within it...

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Verification Effectiveness with Riviera-PRO: SystemVerilog Randomized Layered Testbench
Understanding SystemVerilog Layered Testbench

In this blog, I will discuss randomized layered testbenches used in SystemVerilog. We need to understand why we need it, ...

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Understanding the inner workings of UVM - Part 3
UVM Basics Part 3 of 3

In this blog, I am going to discuss different phases that UVM follows.   The reason why UVM came up with such phases is because synchronization among all design-testbench was necessary. Using Verilog and VHDL,...

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Understanding the inner workings of UVM - Part 2
UVM Basics Part 2 of 3

In this blog, my major focus is on explaining the concepts such as Sequence, Sequencer, Driver and showing how the communication takes place from sequence to sequencer and from sequencer to driver. In the previous blog, I included...

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Partition your Design for FPGA Prototyping
Easily create partitions with HES-DVM

Modern ASIC and SoC designs have increased in complexity such that multiple FPGAs of the largest capacity are now required to prototype the entire functionality of the design. As design sizes increase, more and more...

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