Aldec Design and Verification Blog Trending Articles Do I really need a commercial simulator? Understanding the inner workings of UVM - Part 3 SystemVerilog Functional Coverage in a Nutshell Trace Your Assertions Unit Linting: An easy way to prevent code review issues How to develop an FPGA-based Embedded Vision application for ADAS, series of blogs – Part 1 Understanding the inner workings of UVM - Part 2 All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications Understanding the inner workings of UVM - Part 3 UVM Basics Part 3 of 3 In this blog, I am going to discuss different phases that UVM follows. The reason why UVM came up with such phases is because synchronization among all design-testbench was necessary. Using Verilog and VHDL,... Tags:ASIC,Co-simulation,Coverage,Debugging,Documentation,FPGA,OS-VVM,UVM,Verification Like(0) Comments (3) Read more Understanding the inner workings of UVM - Part 2 UVM Basics Part 2 of 3 In this blog, my major focus is on explaining the concepts such as Sequence, Sequencer, Driver and showing how the communication takes place from sequence to sequencer and from sequencer to driver. In the previous blog, I included... Tags:ASIC,Co-simulation,Coverage,Debugging,Documentation,FPGA,OS-VVM,UVM,Verification Like(2) Comments (0) Read more Partition your Design for FPGA Prototyping Easily create partitions with HES-DVM Modern ASIC and SoC designs have increased in complexity such that multiple FPGAs of the largest capacity are now required to prototype the entire functionality of the design. As design sizes increase, more and more... Tags:ASIC,FPGA,Prototyping,SoC Like(0) Comments (0) Read more Understanding the inner workings of UVM UVM Basics Part 1 of 3 We have all been witnesses to the rapid improvements of the iPhone processor chip every year. With the iPhone 8 featuring the newest A11 Bionic at 10 nm FinFET with 4.3 billion transistors, I can’t personally fathom the amount... Tags:ASIC,Co-simulation,Coverage,Debugging,Documentation,FPGA,OS-VVM,UVM,Verification Like(1) Comments (0) Read more Don’t be a Slave to the Documentation Are you a requirements engineer but your main goal is to provide well organized documentation? Do you have a great knowledge about the industry, business analysis and systems but you are struggling with the shape and look of your documentation?... Tags:ASIC,Documentation,FPGA,Project management Like(0) Comments (0) Read more Austin's Best Vegetarian Restaurants: The Quest Continues If you’re headed to DAC, you should know it's fixing to be the hottest summer ever in Austin, but for brave and hungry meatless eaters, this town is an increasingly cool destination, with creative restauranteurs finding new ways to transform meaty favorites into plant-based edible delights.... Tags:ASIC,Emulation,Verification Like(0) Comments (0) Read more FPGAs in an SoC World How modern FPGA architecture influences verification methodologies The SoC domination observed so far in the ASIC industry is coming to the FPGA world and changing the way FPGAs are used and FPGA projects are verified. The latest SoC FPGA devices ... Tags:ARM,ASIC,FPGA,Hardware-Assisted Verification,Hardware Emulation,Verification Like(3) Comments (1) Read more Software Driven Test of FPGA Prototype Use development software to drive your DUT on an FPGA prototyping platform Most everyone would agree how important FPGA prototyping is to test and validate an IP, sub-system, or a complete SoC design. Before the design is taped-out it can be validated at speeds near real operating conditions with physical peripherals and devices connected to it instead of simulation models. ... Tags:ARM,ASIC,Co-simulation,Design,FPGA,Hardware,Prototyping,SoC,Xilinx Like(2) Comments (0) Read more Aldec Verification Tools Implement the ASIC Verification Flow Insights from Dr. Stanley Hyduke, Aldec Founder and CEO Aldec has, over the last 30 years, established itself as the preferred provider of high-performance, cost-effective verification tools for use in proving out complex FPGA designs. As the logic capacity and capability... Tags:Aceleration,ASIC,Emulation,Linting,Prototyping,Simulation,Verification Like(1) Comments (0) Read more Vegetarian Dining in Austin - DAC 2016 Helpful Tips From a Local I moved to Austin a little over a year ago, and have quickly learned that this city is a progressive blue island in a sea of red. That's the conventional wisdom, and most of the time it holds up.... Tags:ASIC,Emulation,Verification Like(1) Comments (0) Read more
