Aldec Design and Verification Blog Trending Articles Real-time SDR system with TySOM The Convergence of Emulation and Prototyping Development of real-time SDR systems with Aldec HES Performing cross spectrum video processing on a TySOM-3 board How does the Mars Perseverance rover benefit from FPGAs as the main processing units? SynthHESer - Aldec’s New Synthesis Tool Linting RISC-V designs with ALINT-PRO All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications The Convergence of Emulation and Prototyping During the development of a system on chip (SoC), hardware emulation and FPGA prototyping play distinct and essential roles. ● Emulation is used to verify that a design meets its functional requirements, where the verification is performed by emulating the hardware and simulating (using a testbench) the environment in which it must perform.... Tags:ARM,ASIC,Emulation,FPGA,SoC,Validation,Verification Like(3) Comments (0) Read more Linting RISC-V designs with ALINT-PRO As the open-source RISC-V instruction set architecture (ISA) continues to gain momentum, the growing number of RISC-V design solutions, and their flexibility, creates a problem when choosing the most reliable and robust solution from a number of contenders.... Tags:ASIC,FPGA,HDL,Verification,Verilog,Design,Digital,IP,Linting,SoC,SystemVerilog Like(2) Comments (0) Read more Connecting Emulated Design to External PCI Express Device These days verification teams no longer question whether hardware assisted verification should be used in their projects. Rather, they ask at which stage they should start using it. Contemporary System-on-Chip (SoC) designs are already sufficiently complex to make HDL simulation... Tags:ARM,ASIC,Emulation,FPGA,SoC,Validation,Verification Like(2) Comments (0) Read more ARM-based SoC Co-Emulation using Zynq Boards Ready-to-use Co-Emulation Platform Have you ever worked on a group project where you had to combine your work with that of a colleague of a different engineering discipline but the absence of an efficient means of doing so affected the project’s overall outcome?... Tags:ARM,ASIC,Emulation,FPGA,SoC,Validation,Verification,Zynq Like(1) Comments (0) Read more 35-years-old, and still on point At this year’s Design Automation Conference, held on June 3, 4 and 5 in Las Vegas and about 10 miles away from our head office in Las Vegas, Nevada, we celebrated our 35th anniversary with a resounding reaffirmation of our raison d’etre: the provision of verification solutions for some of industry’s most pressing challenges.... Tags:ARM,ASIC,HES,SoC Like(4) Comments (0) Read more The Power of PCIe in Performance-based FPGA World Understanding High speed serial data transfer In today's world, when the entire computing industry is talking about high-performance and high-speed applications using FPGAs, just what are the factors that can assure such performance and speed?... Tags:Aceleration,ASIC,Co-simulation,Documentation,Embedded,Emulation,FPGA,FPGA Simulation,Hardware,HDL,IP,Prototyping,Simulation,SoC,Validation,Verification,Xilinx Like(3) Comments (0) Read more Problems Accessing Registers? – See how UVM RAL can help. As a digital design or verification engineer you know that certain features or configurations of the device can be achieved by programming some registers to set values. For example, a 32-bit register can have several fields within it... Tags:ASIC,Debugging,FPGA,Simulation,SystemVerilog,UVM,Verification Like(2) Comments (0) Read more Verification Effectiveness with Riviera-PRO: SystemVerilog Randomized Layered Testbench Understanding SystemVerilog Layered Testbench In this blog, I will discuss randomized layered testbenches used in SystemVerilog. We need to understand why we need it, ... Tags:Riviera-PRO,ASIC,Assertions,Co-simulation,Coverage,Debugging,Design,Documentation,FPGA,HDL,IEEE,OS-VVM,Randomization,Simulation,standards,SystemVerilog,UVM,Verification,Verilog Like(4) Comments (0) Read more Understanding the inner workings of UVM - Part 3 UVM Basics Part 3 of 3 In this blog, I am going to discuss different phases that UVM follows. The reason why UVM came up with such phases is because synchronization among all design-testbench was necessary. Using Verilog and VHDL,... Tags:ASIC,Co-simulation,Coverage,Debugging,Documentation,FPGA,OS-VVM,UVM,Verification Like(2) Comments (3) Read more Understanding the inner workings of UVM - Part 2 UVM Basics Part 2 of 3 In this blog, my major focus is on explaining the concepts such as Sequence, Sequencer, Driver and showing how the communication takes place from sequence to sequencer and from sequencer to driver. In the previous blog, I included... Tags:ASIC,Co-simulation,Coverage,Debugging,Documentation,FPGA,OS-VVM,UVM,Verification Like(3) Comments (0) Read more
