Aldec Design and Verification Blog

Trending Articles
Acceleration-Ready UVM
Guest Blog by Doulos CTO, John Aynsley

We hear that emulation is one of the fastest-growing segments in EDA right now, yet simulation still continues to be the main workhorse for functional verification, and SystemVerilog and UVM are everywhere you look....

Like(1) Comments (0) Read more
Verifying Large FPGAs Isn't Easy
Guest Blog by Doug Perry, Senior Member Technical Staff at Doulos

The latest crop of FPGA devices are enormous when compared to ASICs that were built not that long ago. Verifying these ASICs required detailed plans, multiple tools, and sometimes special languages....

Like(1) Comments (0) Read more
‘Don’t Be Afraid of UVM’ Webinar on YouTube
Free webinar from the Aldec archives

Just in time for Halloween, Aldec has released a popular past webinar Don’t be Afraid of UVM for Hardware Designers on YouTube. Designers are usually very busy doing their work and have little time left for experimentation...

Like(1) Comments (0) Read more
SVUnit Adds Support for Aldec Riviera-PRO Users
A Guest Blog by Neil Johnson, HW Engineer/ Co-Moderator

As I wrote on recently, Aldec users have something to get excited about as SVUnit now supports Riviera-PRO™, Aldec’s advanced verification platform. SVUnit is an open-source test framework for ASIC and FPGA developers...

Like(1) Comments (0) Read more
Visualizing UVM Environments: Debug Features Deliver a Clearer View
Guest Blog from Srinivasan Venkataramanan of CVC

It is an often-quoted statistic that Functional Verification consumes the lion’s share (40-70%) of ASIC and complex FPGA design projects. A less often stated fact, yet no less true, is the majority of verification cycle time is spent...

Like(2) Comments (0) Read more
Integrating SystemVerilog and SCE-MI for Faster Emulation Speed
Developing your own Emulation API

In the last SCE-MI article, we discussed how SCE-MI macro-based infrastructures can speedup SoC design verification time. In SCE-MI 2.1, Accelera introduced a ‘function-based’ infrastructure...

Like(1) Comments (0) Read more
HW Designers: Brush up on your SV with Online Training
Fast Track to SystemVerilog for Verilog Users

The ability to adopt methodologies and get up to speed quickly is critical in today’s fast moving environment. Aldec offers Fast Track™ ONLINE trainings designed for busy engineers to increase their productivity and ...

Like(0) Comments (0) Read more
Riviera-PRO 2013.06 Enables Class Hierarchy Visualization
For UVM-Based Verification Environments

As Product Manager, I am especially pleased with the level of increased verification productivity we are delivering in the most recent release, Riviera-PRO™ 2013.06.  In particular, verification teams will find the new class hierarchy visualization for ...

Like(1) Comments (0) Read more
Wait….Did you say HDL Editor?
Productivity Boosting Features

Yes I did, but with no intention to start a holy war on which HDL editor is best. When it comes to HDL editors, each engineer has their own choice and I am not attempting to hurt any madly, deeply felt sentiments. My goal is only to bring the awareness to those using the HDL editor built into Active-HDL™ and...

Like(1) Comments (0) Read more
Back from DAC
Functional Verification Insights from Austin

I just returned  back to the office from the 50th Design Automation Conference (DAC) which took place in Austin, TX, on June 2—6. As I began compiling my trip report, I thought that I might share some of my observations, especially for those who couldn’t attend this industry event but still wanted to gain some insight....

Like(2) Comments (0) Read more
Ask Us a Question

Ask Us a Question

Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.