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Zynq-based Embedded Development Kit for University Programs
Cost-effective solution for HW/SW development projects

Creativity and innovation, which lead the society to success, rest on the foundational institutions such as schools and universities. They provide fertile soil to seed, grow and flourish enterprises....

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Synthesis of Energy-Efficient FSMs Implemented in PLD Circuits
Finite State Machines in low-power world

Well, summer has been and gone; and for most of us it was a time to relax and reflect on our working practices. What can we do to achieve better results? And what can we do to break out of the routine of working on so many revisions?...

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Reprogrammable, reprogrammable, reprogrammable: What’s great about FPGAs!
Guest Blog by Alex Grove, Applications Specialist at FirstEDA

I like FPGAs. My first experience with an FPGA was my university final year project where I demonstrated BIST with four Xilinx© 3000 devices; this was before FPGAs had JTAG built in. Filling up these devices...

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Why Digital Design Students choose Active-HDL™
Mixed-language simulation for VHDL-2008, Verilog and SystemVerilog (Design)

Active-HDL™ STUDENT EDITION is a popular solution for university students looking to enhance their digital design learning experience. A mixed-language simulator that supports VHDL-2008,...

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90’s Kid Active-HDL Celebrates Sweet 16
Serving FPGA Designers as the tool of choice since, like, forever

As the proud Product Manager of Aldec’s  FPGA Design Simulation solution,  I am excited (like it was my first Cranberries concert) to announce that Active-HDL™ is celebrating 16 years since its initial release in 1997....

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