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UVM Register Layer: The Structure
Creating an anatomically correct model for poking and prodding.

I don’t know about you, but I am looking forward to the day where we won’t even have to go to the doctor’s office for an exam. Instead, we will all have scanners in our homes that will transmit full digital models to our doctors...

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Transitioning to Advanced Verification Techniques for FPGAs – Catch-22?
A Guest Blog by TVS Founder and CEO, Dr. Mike Bartley

Many FPGA designers find themselves in a catch-22: they recognise that their designs are becoming too complex for their current verification strategies BUT adopting advanced verification techniques (such as the Universal Verification Methodology – UVM) is...

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SVUnit Adds Support for Aldec Riviera-PRO Users
A Guest Blog by Neil Johnson, HW Engineer/AgileSoC.com Co-Moderator

As I wrote on AgileSoC.com recently, Aldec users have something to get excited about as SVUnit now supports Riviera-PRO™, Aldec’s advanced verification platform. SVUnit is an open-source test framework for ASIC and FPGA developers...

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The Future of EDA?
A Guest Blog by Chris Higgs of Potential Ventures

I'm not the first engineer to suggest that utilising Python for verification could be a big leap forward for the EDA industry.  The big vendors haven’t (yet) embraced this suggestion, so why am I still convinced Python is the way forward?...

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90’s Kid Active-HDL Celebrates Sweet 16
Serving FPGA Designers as the tool of choice since, like, forever

As the proud Product Manager of Aldec’s  FPGA Design Simulation solution,  I am excited (like it was my first Cranberries concert) to announce that Active-HDL™ is celebrating 16 years since its initial release in 1997....

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HW Designers: Brush up on your SV with Online Training
Fast Track to SystemVerilog for Verilog Users

The ability to adopt methodologies and get up to speed quickly is critical in today’s fast moving environment. Aldec offers Fast Track™ ONLINE trainings designed for busy engineers to increase their productivity and ...

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Legacy Schematic Designs Giving you a Headache?
Retargeting Legacy Designs for New Technology

Digital design has come a long way since its inception from drawing schematic on paper, to CAD tools which can be used to draw schematics, and to today’s most popular (and efficient) process of describing designs through HDLs....

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Wait….Did you say HDL Editor?
Productivity Boosting Features

Yes I did, but with no intention to start a holy war on which HDL editor is best. When it comes to HDL editors, each engineer has their own choice and I am not attempting to hurt any madly, deeply felt sentiments. My goal is only to bring the awareness to those using the HDL editor built into Active-HDL™ and...

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Back from DAC
Functional Verification Insights from Austin

I just returned  back to the office from the 50th Design Automation Conference (DAC) which took place in Austin, TX, on June 2—6. As I began compiling my trip report, I thought that I might share some of my observations, especially for those who couldn’t attend this industry event but still wanted to gain some insight....

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Xilinx Opens Their IP for Simulation with Aldec Flow
Using P1735 Interoperable Encryption Standard

As we know, the first industry standard trying to solve the Intellectual Property (IP) delivery problem was Verilog-2005. It contained sound theoretical description but lacked some practical usage guidelines needed to create interoperable implementations. VHDL-2008 standard, based on the same donation by...

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