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What is Bird’s Eye View ADAS Application and How to Develop This Using Zynq® UltraScale+™ MPSoC FPGA?
Bird’s eye view definition, HW/SW setup and implementation algorithms

Will the world be a better place in which to live by having autonomous cars driving around us? Or would it be unsafe and scary? Maybe someone was asking such a question even when the first steam-powered automobile capable...

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HW/SW Co-Simulation for SoC FPGA designs
Aldec’s Co-Simulation Solution using QEMU and Riviera-PRO

Heterogeneous System on Chip (SoC) devices like the Xilinx Zynq 7000 and Zynq UltraScale+ MPSoC combine a high-performance processing system (PS) with state-of-the-art programmable logic (PL)....

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The Race to Zero Latency for High Frequency Trading

The High-Frequency Trading (HFT) industry has received a lot of attention during the last few years. HFT is all about speed and minimizing latency: the faster you can run trading strategies and algorithms for analyzing minute price changes...

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FPGA vs GPU for Machine Learning Applications: Which one is better?
Can FPGAs beat GPUs?

FPGAs or GPUs, that is the question.   Since the popularity of using machine learning algorithms to extract and process the information from raw data, it has been a race between FPGA and GPU vendors to offer...

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Verification Effectiveness with Riviera-PRO: SystemVerilog Randomized Layered Testbench
Understanding SystemVerilog Layered Testbench

In this blog, I will discuss randomized layered testbenches used in SystemVerilog. We need to understand why we need it, ...

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How to develop an FPGA-based Embedded Vision application for ADAS, series of blogs – Part 1
FPGA “The winner for the low-power and high-performance vision-based applications”

When should we use the term “Vision for Everything”, as vision-based applications are entering various industries? It’s been a few years since the emergence of...

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Code Coverage in HDL Editor? Now That’s a Nice Feature.

For a long time I have been a fan of code coverage tools that are embedded into the simulators themselves, and which give you the ability to switch easily between the code and the coverage results. It is particularly helpful to have a way...

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UVM Register Layer: The Structure
Creating an anatomically correct model for poking and prodding.

I don’t know about you, but I am looking forward to the day where we won’t even have to go to the doctor’s office for an exam. Instead, we will all have scanners in our homes that will transmit full digital models to our doctors...

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Transitioning to Advanced Verification Techniques for FPGAs – Catch-22?
A Guest Blog by TVS Founder and CEO, Dr. Mike Bartley

Many FPGA designers find themselves in a catch-22: they recognise that their designs are becoming too complex for their current verification strategies BUT adopting advanced verification techniques (such as the Universal Verification Methodology – UVM) is...

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SVUnit Adds Support for Aldec Riviera-PRO Users
A Guest Blog by Neil Johnson, HW Engineer/AgileSoC.com Co-Moderator

As I wrote on AgileSoC.com recently, Aldec users have something to get excited about as SVUnit now supports Riviera-PRO™, Aldec’s advanced verification platform. SVUnit is an open-source test framework for ASIC and FPGA developers...

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