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Verification Effectiveness with Riviera-PRO: SystemVerilog Randomized Layered Testbench
Understanding SystemVerilog Layered Testbench

In this blog, I will discuss randomized layered testbenches used in SystemVerilog. We need to understand why we need it, ...

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Understanding the inner workings of UVM - Part 3
UVM Basics Part 3 of 3

In this blog, I am going to discuss different phases that UVM follows.   The reason why UVM came up with such phases is because synchronization among all design-testbench was necessary. Using Verilog and VHDL,...

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Understanding the inner workings of UVM - Part 2
UVM Basics Part 2 of 3

In this blog, my major focus is on explaining the concepts such as Sequence, Sequencer, Driver and showing how the communication takes place from sequence to sequencer and from sequencer to driver. In the previous blog, I included...

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Understanding the inner workings of UVM
UVM Basics Part 1 of 3

We have all been witnesses to the rapid improvements of the iPhone processor chip every year. With the iPhone 8 featuring the newest A11 Bionic at 10 nm FinFET with 4.3 billion transistors, I can’t personally fathom the amount...

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Beer, Cars, and Verification
My thoughts after DVCon Europe

As I write this, I am visiting the Aldec corporate office in the US on the day following their historical presidential election. It’s been a busy travel season for this product manager, and only a few weeks ago I was at DVCon Europe in Munich - the city of pork knuckles, beer... and of course, cars. ...

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The 80s music at DAC was my idea. You're welcome.
DAC Chats to be presented live online

If you attended the Monday Night Reception at DAC 2014, you were greeted with a blast of 80s pop music. If you then said to yourself, “I’d like to meet the genius behind that idea” - that would be me. A few weeks before DAC...

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My First Example with OS-VVM CoveragePkg
A Guest Blog from Alex Grove of FirstEDA

Here in Europe, I recently had the opportunity to work with Jim Lewis, OS-VVM Chief Architect and IEEE 1076 Working Group Chair, on the first Advanced VHDL Testbenches & Verification training course....

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Why Randomize?
Guest Blog with Jim Lewis, VHDL Training Expert at SynthWorks

After presenting a conference paper on how to do OSVVM-style constrained random and intelligent coverage (randomization based on functional coverage holes), I received  a great question, "Why Randomize?"...

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90’s Kid Active-HDL Celebrates Sweet 16
Serving FPGA Designers as the tool of choice since, like, forever

As the proud Product Manager of Aldec’s  FPGA Design Simulation solution,  I am excited (like it was my first Cranberries concert) to announce that Active-HDL™ is celebrating 16 years since its initial release in 1997....

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