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Zynq-based Embedded Development Kit for University Programs
Cost-effective solution for HW/SW development projects

Creativity and innovation, which lead the society to success, rest on the foundational institutions such as schools and universities. They provide fertile soil to seed, grow and flourish enterprises....

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Software Driven Test of FPGA Prototype
Use development software to drive your DUT on an FPGA prototyping platform

Most everyone would agree how important FPGA prototyping is to test and validate an IP, sub-system, or a complete SoC design. Before the design is taped-out it can be validated at speeds near real operating conditions with physical peripherals and devices connected to it instead of simulation models. ...

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Leveraging the Power of VDMA Engines for Computer Vision Apps with TySOM™ - Part 1
In-depth Overview of VDMA Use Cases for TySOM™ Reference Designs

It's pretty hard to overestimate the role of heterogeneous embedded systems based on Xilinx® Zynq®-7000 All-Programmable devices in tasks like computer vision. Many consumer electronics and specialized devices are emerging to facilitate and improve industries such as medical, automotive, security, and IoT. Aldec ...

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Leveraging the Power of VDMA Engines for Computer Vision Apps with TySOM™ - Part 2
In-depth Overview of VDMA Use Cases for TySOM™ Reference Designs

In a previous blog, I reviewed how Xilinx VDMA cores can be used for frame grabbing tasks with digital cameras based on commonly used DVP and MIPI CSI-2 video data interfaces. Now it's time to shed some light on the other side of the subject. ...

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‘Don’t Be Afraid of UVM’ Webinar on YouTube
Free webinar from the Aldec archives

Just in time for Halloween, Aldec has released a popular past webinar Don’t be Afraid of UVM for Hardware Designers on YouTube. Designers are usually very busy doing their work and have little time left for experimentation...

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Helping FPGA Designers get started with UVM
Guest Blog by Doulos CTO, John Aynsley

UVM (the Universal Verification Methodology for SystemVerilog) represents best practice in constrained random functional verification, so it is something that every digital design and verification engineer should be aware of....

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Webinars, YouTube, Articles... What’s your preference?
Useful resources to help you get ahead

“USEFUL” is a word you’ll hear a lot over here at Aldec. It’s the number one way we rank our success when developing a new product or feature. “How USEFUL is it?” is the most common phrase we challenge one another...

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Averting CDC Roadblocks in FPGA Design
Design Rule Checking Best Practices

This being my first summer in Las Vegas, it is the first time I’ve experienced the rainy, desert monsoon season and the powerful flash floods it can bring. Last week one of those monsoons, powered by the remnants of Hurricane Norbert,...

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Stress-Relief for Requirements-Based Verification
Verification of Safety-Critical FPGAs under Strict DO-254 Guidance

If they’re being honest, anyone who has verified an FPGA under strict DO-254 guidance will tell you that it is stressful. Show me an engineer on their first DO-254 project – and I’ll show you someone pulling out their hair...

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DO-254/CTS™ solves Elbit’s major challenges
Helps them pass EASA Verification Audit

Aldec has been working closely with Elbit Systems in Israel on an important DO-254 project for some time now. Using Aldec’s specialized solution DO-254/CTS™ as their primary FPGA physical testing platform,...

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