Accelerating Simulation of Vivado Designs with HES

Improve verification speedup with Aldec’s HES-DVM

Krzysztof Szczur, Hardware Verification Products Manager
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FPGA Design Verification Challenge

The FPGA design and verification “ecosystem” changes rapidly to keep pace with the fast growing size of FPGA devices. The largest Xilinx Virtex UltraSCALE chips provide 4.4 Million logic cells or using another metric 50 million equivalent gate count.

 

To enable efficient design process for Virtex-7 and newer UltraSCALE FPGAs, Xilinx provides software called Vivado Design Suite. Besides supporting a classical HDL design flow, it also provides system level design tools like IP Integrator, System Generator or even High Level Synthesis, that are very convenient for designing large and complex designs.

 

Verification has always taken a significant share of the project schedule with HDL simulation being the main stage of that process. With such big designs however, even the fastest simulators would spend hours in simulation tasks.

 

Simulation Acceleration with HES-DVM™

Aldec's HES-DVM bridges this gap enabling accelerated simulation with the design running in the FPGA and the testbench in the simulator.

 

Aldec has been providing HES™ - Hardware Emulation Solutions since 2001. During that time the HES evolved to address the most sophisticated design requirements and fulfill customers’ requirements. Thus, simulation acceleration is only one example of how HES can be used with other applications being hybrid co-emulation, in circuit emulation, and physical prototyping.>

 

With simulation acceleration the user can move any synthesizable module from simulator to the FPGA thus offload some processing from the HDL simulator. Typically, an entire design is implemented in HES board and the simulator only executes the testbench.

 

Figure 1: Signal-level simulation acceleration

 

The HES boards are seamlessly integrated with the simulator with PCI Express x8 physical connection to the host workstation. The HES-DVM provides co-simulation interfaces for Aldec's Riviera-PRO and Active-HDL simulators but also for other 3rd party simulators. It can be used both in Linux and Windows operating systems with all required PCIe drivers and interfaces working out of the box.

 

The DVM tool automates the process of design compilation and implementation for HES boards. It generates all necessary scripts and configuration files to run simulation acceleration in a given HES board but also brings many useful debugging features. Despite running your design in FPGA hardware you can keep simulation level visibility with an RTL View of all internal probes.

 

Figure 2: Design Setup Flow for Acceleration using DVM™

 

Acceleration Benchmark

How much acceleration can I achieve? This is always the first customer’s question and frankly there is no straight answer because the result depends on the complexity of both the design and the testbench. Usually a good estimation can be obtained from running simulation profiling and then applying Amdahl’s rule. However, the best way to verify acceleration potential is just to experiment with a typical design, so we have created a simple design of a memory sub-system using Xilinx Vivado Design environment. It contains MIG controller for DDR3, AXI interconnect, two AXI traffic generators and one AXI protocol checker as shown in the following diagram.

 

Figure 3. Memory subsystem diagram created for benchmarking

 

Benchmark Results

Riviera-PRO Riviera-PRO + HES
  Wall-clock time 1537 seconds 3 seconds
  Acceleration ratio
512

 

Workstation and software used for benchmarking:

 

Workstation:

CPU: Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz

RAM: 32 GB

HES Board: HES7XV4000BP_REV2, contains 2x Virtex7 2000 FPGA

 

Software:

OS: Linux CentOS 6, x86_64

Simulator: Riviera-PRO 2017.02

Design env: Vivado 2016.4

Acceleration env: HES-DVM 2017.02

 

If you are interested in further details about this project, benchmark, and tools which can significantly accelerate your simulation you can view the following application note: https://www.aldec.com/en/support/resources/documentation/articles/1915

Krzysztof joined Aldec in 2001 and was a key member of the team that developed HES-DVM™, Aldec's FPGA-based simulation acceleration and emulation technology. He has worked in the fields of HDL IP-core verification, testbench automation and design verification for DO-254 compliance gaining practical experience and deep understanding of design verification methodologies, emulation and physical prototyping. As Hardware Verification Products Manager, Krzysztof cooperates with key customers and Aldec's R&D to overcome complex design verification challenges using Aldec hardware tools and solutions. Krzysztof graduated as M.Eng. in Electronic Engineering (EE) at the AGH University of Science and Technology in Krakow, Poland

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