Aldec Design and Verification Blog Trending Articles No Risk No Fun What is Bird’s Eye View ADAS Application and How to Develop This Using Zynq® UltraScale+™ MPSoC FPGA? HW/SW Co-Simulation for SoC FPGA designs The Power of PCIe in Performance-based FPGA World Problems Accessing Registers? – See how UVM RAL can help. The Race to Zero Latency for High Frequency Trading Verification Effectiveness with Riviera-PRO: SystemVerilog Randomized Layered Testbench All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications What is Bird’s Eye View ADAS Application and How to Develop This Using Zynq® UltraScale+™ MPSoC FPGA? Bird’s eye view definition, HW/SW setup and implementation algorithms Will the world be a better place in which to live by having autonomous cars driving around us? Or would it be unsafe and scary? Maybe someone was asking such a question even when the first steam-powered automobile capable... Tags:Aceleration,ARM,Embedded,FPGA,Hardware,HDL,Prototyping,Validation,Verification,Verilog,Design,Digital,SoC,Xilinx,Zynq Like(0) Comments (0) Read more HW/SW Co-Simulation for SoC FPGA designs Aldec’s Co-Simulation Solution using QEMU and Riviera-PRO Heterogeneous System on Chip (SoC) devices like the Xilinx Zynq 7000 and Zynq UltraScale+ MPSoC combine a high-performance processing system (PS) with state-of-the-art programmable logic (PL).... Tags:Co-simulation,Embedded,FPGA,Hardware,HDL,Simulation,SoC,Validation,Verification,Verilog,VHDL,Xilinx Like(1) Comments (0) Read more The Power of PCIe in Performance-based FPGA World Understanding High speed serial data transfer In today's world, when the entire computing industry is talking about high-performance and high-speed applications using FPGAs, just what are the factors that can assure such performance and speed?... Tags:Aceleration,ASIC,Co-simulation,Documentation,Embedded,Emulation,FPGA,FPGA Simulation,Hardware,HDL,IP,Prototyping,Simulation,SoC,Validation,Verification,Xilinx Like(2) Comments (0) Read more FPGA vs GPU for Machine Learning Applications: Which one is better? Can FPGAs beat GPUs? FPGAs or GPUs, that is the question. Since the popularity of using machine learning algorithms to extract and process the information from raw data, it has been a race between FPGA and GPU vendors to offer... Tags:Aceleration,Embedded,FPGA,Hardware,HDL,Validation,Verilog,VHDL,Xilinx Like(1) Comments (0) Read more Aldec and NEC reveal HLS shortcut at upcoming SoC Conference Breaking through the growing design verification maze The University of California, Irvine (UCI) is popular for many things, but I recall during my school days that it was distinctly known among students for its underground tunnel network.... Tags:SoC,Prototyping,ASIC,Validation,Verification Like(1) Comments (0) Read more SCE-MI for SoC Verification Transaction-level Interface Delivers Performance Today’s System-on-Chip verification teams are moving up in the levels of abstraction to increase the degree of coverage in the system design. As designs grow larger,... Tags:Co-simulation,Emulation,FPGA,Hardware,SoC,Validation,Verification Like(1) Comments (0) Read more The WHAT is mandatory but the HOW is entirely optional Intro to High Level Synthesis You look confused. Perhaps I owe you an explanation. Anyone familiar with hardware design flow knows that it starts with specification and ends with implementation. The specification in this flow is the “What” – it defines what needs to be designed.... Tags:Design,SoC,SystemC,Validation,Verification Like(0) Comments (0) Read more The Magic of CyberWorkBench Why you should take a closer look My first encounter with NEC’s CyberWorkBench (CWB) was in 2003 while attending DAC. Like most people, I was surprised to see a big Japanese company offering EDA tools.... Tags:Design,SoC,SystemC,Validation,Verification Like(1) Comments (0) Read more ASIC/FPGA High Level Synthesis Solution from NEC CyberWorkBench joins Aldec’s Verification Ecosystem Aldec (tried to) quietly introduce our new friends from NEC Japan for the first time at DAC this year. They joined us in our booth in Austin and were soon the life of the party as many people were eager to learn... Tags:Design,SoC,Verification,SystemC,Validation Like(1) Comments (0) Read more Time-Saving, Hardware-assisted Verification For ASIC/SoC Designs Identifying effective processes for functional verification of ASIC and SoC designs is of increased significance for engineers due to growing design complexity and integration of embedded components such as CPUs, GPUs, and software device drivers. Overall test time for these systems can include millions... Tags:HES,Emulation,Aceleration,ASIC,SoC,Design,Validation,Verification,Prototyping,Debugging Like(0) Comments (0) Read more
