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Transitioning to Advanced Verification Techniques for FPGAs – Catch-22?
A Guest Blog by TVS Founder and CEO, Dr. Mike Bartley

Many FPGA designers find themselves in a catch-22: they recognise that their designs are becoming too complex for their current verification strategies BUT adopting advanced verification techniques (such as the Universal Verification Methodology – UVM) is...

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Driving Innovation in Image Sensors and High Speed Analog/Mixed-Signal Design
Guest Blog with John Zuk from Tanner EDA

Aldec Product Manager, Dmitry Melnik, recently shared a blog update on Verilog-AMS & Multi-Level Simulation. Within the many inquiries he mentions, we noted a consistent theme...

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Verilog-AMS & Multi-Level Simulation
Aldec and Tanner EDA Bridge Digital and Analog Design Flows

It occurred to me that it has been a few months since we shared an update on HiPer Simulation A/MS. Following DAC 2013 and Daniel Payne’s posts at SemiWiki (post 1, post 2),...

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90’s Kid Active-HDL Celebrates Sweet 16
Serving FPGA Designers as the tool of choice since, like, forever

As the proud Product Manager of Aldec’s  FPGA Design Simulation solution,  I am excited (like it was my first Cranberries concert) to announce that Active-HDL™ is celebrating 16 years since its initial release in 1997....

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