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The UVM Configuration Database
Keeping a neat repository for flexible testbench structure

When I want to wear a certain clothing item, I take out it of the closet. When I go shopping, I add those clothes it to my closet and there are now new items for me to pick out in the future....

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Aldec Verification Tools Implement the ASIC Verification Flow
Insights from Dr. Stanley Hyduke, Aldec Founder and CEO

Aldec has, over the last 30 years, established itself as the preferred provider of high-performance, cost-effective verification tools for use in proving out complex FPGA designs. As the logic capacity and capability...

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UVM Register Layer: The Structure
Creating an anatomically correct model for poking and prodding.

I don’t know about you, but I am looking forward to the day where we won’t even have to go to the doctor’s office for an exam. Instead, we will all have scanners in our homes that will transmit full digital models to our doctors...

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A Winning HDL Design Strategy
Installing Vivado libraries in your Active-HDL™ design

In a basketball game, a winning strategy is not only to have a good team, but to have a good game plan as well. In HDL terms, a good design is just as important as the libraries that it uses....

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Extend Vivado Capabilities with Help From the Tcl Store
Xilinx Vivado Tutorial: Upgrade for increased simulation performance

Outgrowing something can be hard. So hard, that sometimes we live in denial longer than we should. We are resistant to change, often because we are simply too comfortable with what we know (or too busy) to consider the options....

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So, what does a vendor-independent simulator look like?
Tackle your next FPGA design with Active-HDL ™

Well, the short answer to that is, “Awesome”. Perhaps, as the product manager of a simulation tool, I’m a little biased. Not to discount the challenges that FPGA design teams face on daily basis,...

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Xilinx Tcl Store Integrates Aldec Simulators with Vivado IDE
App now integrates Active-HDL & Riviera-PRO

Taking a cue from the open-source community, Xilinx has launched a Tcl Store that aggregates Tcl scripts contributed by the greater development community to expand the capabilities of the Vivado® Integrated Design Environment....

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Transitioning to Advanced Verification Techniques for FPGAs – Catch-22?
A Guest Blog by TVS Founder and CEO, Dr. Mike Bartley

Many FPGA designers find themselves in a catch-22: they recognise that their designs are becoming too complex for their current verification strategies BUT adopting advanced verification techniques (such as the Universal Verification Methodology – UVM) is...

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Averting CDC Roadblocks in FPGA Design
Design Rule Checking Best Practices

This being my first summer in Las Vegas, it is the first time I’ve experienced the rainy, desert monsoon season and the powerful flash floods it can bring. Last week one of those monsoons, powered by the remnants of Hurricane Norbert,...

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Want to be a Verification Engineer? Practice. Practice. Practice.
Simulate UVM & SystemVerilog online for free

HDL design and verification engineers are being absorbed by the job market faster than universities can create them. The desperation of high tech firms is evident in aggressive job posts offering paid relocation, bonuses and other incentives....

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