Aldec Design and Verification Blog Trending Articles Bridging Simulation and Hardware Advanced Static Linting for FPGA Performance Optimization Scalable Cloud-based CI/CD HDL Verification Environment Navigating VUnit: A Practical Guide to Modifying Testing Approaches Speeding Up Simulation with VUnit for Parallel Testing Introduction to VUnit FPGA Design Verification in a Nutshell All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications Bridging Simulation and Hardware Hardware-in-the-Loop in Action Whether developing FPGAs, ASICs, or AI-enabled embedded systems, verification remains one of the most challenging and time-consuming phases of the development process. Hardware-in-the-Loop (HIL) testing is transforming this process.... Tags:Aceleration,Embedded,FPGA,Hardware,HDL,Prototyping,Simulation,Xilinx,Design Like(0) Comments (0) Read more Advanced Static Linting for FPGA Performance Optimization How to Boost Design Speed and Efficiency Accelerate FPGA Design with Advanced Static Linting In modern high-speed FPGA design, raw performance isn’t enough. Engineers face increasing challenges in achieving higher clock frequencies, lower power consumption, and smaller silicon footprints... Tags:FPGA,Prototyping,FPGA Simulation,Design,Hardware,HDL,Linting,safety-critical,Simulation,STARC,Verification,Xilinx Like(0) Comments (0) Read more Scalable Cloud-based CI/CD HDL Verification Environment Enhance Your Verification Workflow with Azure, VUnit, and Riviera-PRO Verification is the cornerstone of digital design, ensuring high reliability and functional correctness of FPGA and SoC designs. By integrating Azure’s scalable cloud computing, the open-source unit testing capabilities of VUnit, and the high-performance simulation engine of Riviera-PRO,... Tags:Aceleration,Functional Verification,HDL,Riviera-PRO,Simulation,Verification,VHDL Like(0) Comments (0) Read more Navigating VUnit: A Practical Guide to Modifying Testing Approaches In the two previous blogs, we introduced you to the world of VUnit, guided you through creating a project from scratch, and demonstrated how to run multi-threaded unit testing of multiple independent tests.... Tags:Aceleration,Functional Verification,HDL,Riviera-PRO,Simulation,Verification,VHDL Like(0) Comments (0) Read more Development of real-time SDR systems with Aldec HES As telecommunication technologies evolve there is an on-going drive for the development of high-performance systems for radio communications. Part of that evolution involves implementing components in software functions that had traditionally been implemented in hardware.... Tags:Aceleration,FPGA,Hardware,HDL,Prototyping,Simulation,Xilinx,Design Like(8) Comments (7) Read more HW/SW Co-Simulation for SoC FPGA designs Aldec’s Co-Simulation Solution using QEMU and Riviera-PRO Heterogeneous System on Chip (SoC) devices like the Xilinx Zynq 7000 and Zynq UltraScale+ MPSoC combine a high-performance processing system (PS) with state-of-the-art programmable logic (PL).... Tags:Co-simulation,Embedded,FPGA,Hardware,HDL,Simulation,SoC,Validation,Verification,Verilog,VHDL,Xilinx Like(2) Comments (0) Read more The Power of PCIe in Performance-based FPGA World Understanding High speed serial data transfer In today's world, when the entire computing industry is talking about high-performance and high-speed applications using FPGAs, just what are the factors that can assure such performance and speed?... Tags:Aceleration,ASIC,Co-simulation,Documentation,Embedded,Emulation,FPGA,FPGA Simulation,Hardware,HDL,IP,Prototyping,Simulation,SoC,Validation,Verification,Xilinx Like(3) Comments (0) Read more Problems Accessing Registers? – See how UVM RAL can help. As a digital design or verification engineer you know that certain features or configurations of the device can be achieved by programming some registers to set values. For example, a 32-bit register can have several fields within it... Tags:ASIC,Debugging,FPGA,Simulation,SystemVerilog,UVM,Verification Like(2) Comments (0) Read more Verification Effectiveness with Riviera-PRO: SystemVerilog Randomized Layered Testbench Understanding SystemVerilog Layered Testbench In this blog, I will discuss randomized layered testbenches used in SystemVerilog. We need to understand why we need it, ... Tags:Riviera-PRO,ASIC,Assertions,Co-simulation,Coverage,Debugging,Design,Documentation,FPGA,HDL,IEEE,OS-VVM,Randomization,Simulation,standards,SystemVerilog,UVM,Verification,Verilog Like(4) Comments (0) Read more Do I really need a commercial simulator? A quick view of the benefits of a commercial simulator As an Applications Engineer I visit lots of potential customers, or talk to them at trade shows, who are doing FPGA designs but don’t own a commercial simulator. I ask them why that is. Most of the time it is budgetary restrictions. They don’t... Tags:Debugging,Design,Simulation,Verification Like(1) Comments (0) Read more
