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Plots: A New Way To Analyze Data

Data analysis is often a very time consuming process for a hardware design or verification engineer. We always end up using the waveform viewer which may not be very efficient in giving us a high-level overview of what we’re looking for. Data that is spread across...

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Zynq-based Embedded Development Kit for University Programs
Cost-effective solution for HW/SW development projects

Creativity and innovation, which lead the society to success, rest on the foundational institutions such as schools and universities. They provide fertile soil to seed, grow and flourish enterprises....

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Accelerating Simulation of Vivado Designs with HES
Improve verification speedup with Aldec’s HES-DVM

FPGA Design Verification Challenge The FPGA design and verification “ecosystem” changes rapidly to keep pace with the fast growing size of FPGA devices. The largest Xilinx Virtex UltraSCALE chips provide 4.4 Million logic cells...

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VHDL-2017: Some of My Favorite Things

For the past several years I have had the privilege to chair the IEEE 1076 VHDL working group. In March we handed off the revisions to the VHDL LRM to our technical editor to finalize the document for balloting. As we are waiting for the standards process to finish up, I thought I would share my favorite new additions. Let me start with an executive summary: ...

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The UVM Configuration Database
Keeping a neat repository for flexible testbench structure

When I want to wear a certain clothing item, I take out it of the closet. When I go shopping, I add those clothes it to my closet and there are now new items for me to pick out in the future....

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Aldec Verification Tools Implement the ASIC Verification Flow
Insights from Dr. Stanley Hyduke, Aldec Founder and CEO

Aldec has, over the last 30 years, established itself as the preferred provider of high-performance, cost-effective verification tools for use in proving out complex FPGA designs. As the logic capacity and capability...

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UVM Register Layer: The Structure
Creating an anatomically correct model for poking and prodding.

I don’t know about you, but I am looking forward to the day where we won’t even have to go to the doctor’s office for an exam. Instead, we will all have scanners in our homes that will transmit full digital models to our doctors...

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A Winning HDL Design Strategy
Installing Vivado libraries in your Active-HDL™ design

In a basketball game, a winning strategy is not only to have a good team, but to have a good game plan as well. In HDL terms, a good design is just as important as the libraries that it uses....

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Extend Vivado Capabilities with Help From the Tcl Store
Xilinx Vivado Tutorial: Upgrade for increased simulation performance

Outgrowing something can be hard. So hard, that sometimes we live in denial longer than we should. We are resistant to change, often because we are simply too comfortable with what we know (or too busy) to consider the options....

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So, what does a vendor-independent simulator look like?
Tackle your next FPGA design with Active-HDL ™

Well, the short answer to that is, “Awesome”. Perhaps, as the product manager of a simulation tool, I’m a little biased. Not to discount the challenges that FPGA design teams face on daily basis,...

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