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Code Coverage in HDL Editor? Now That’s a Nice Feature.

For a long time I have been a fan of code coverage tools that are embedded into the simulators themselves, and which give you the ability to switch easily between the code and the coverage results. It is particularly helpful to have a way...

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Understanding the inner workings of UVM
UVM Basics Part 1 of 3

We have all been witnesses to the rapid improvements of the iPhone processor chip every year. With the iPhone 8 featuring the newest A11 Bionic at 10 nm FinFET with 4.3 billion transistors, I can’t personally fathom the amount...

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A Comprehensive RTL Verification Solution for VHDL
ALINT-PRO™ Design Rule Checking Solution

On Thursday, November 19, I’ll be hosting a webinar to demonstrate Aldec’s RTL Verification Solution for VHDL, ALINT-PRO™ Design Rule Checking Solution.   ALINT-PRO is Aldec’s design verification solution for RTL code...

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Code Coverage – Can we get a little help here?
Productivity boost from Condition and Path Coverage

Don’t get me wrong, coverage analysis has been used by engineers for years now and it usefulness in improving productivity and verification environment quality can’t be stressed enough....

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Transitioning to Advanced Verification Techniques for FPGAs – Catch-22?
A Guest Blog by TVS Founder and CEO, Dr. Mike Bartley

Many FPGA designers find themselves in a catch-22: they recognise that their designs are becoming too complex for their current verification strategies BUT adopting advanced verification techniques (such as the Universal Verification Methodology – UVM) is...

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Stress-Relief for Requirements-Based Verification
Verification of Safety-Critical FPGAs under Strict DO-254 Guidance

If they’re being honest, anyone who has verified an FPGA under strict DO-254 guidance will tell you that it is stressful. Show me an engineer on their first DO-254 project – and I’ll show you someone pulling out their hair...

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Averting Clock-Domain Crossing issues in FPGA Design
A solution to your worst CDC nightmare

A failing FPGA device in the field with a Clock Domain Crossing (CDC) issue is a true nightmare. The risk of CDC related failure is on the rise as FPGA-based SOC design complexity continues to mount...

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My First Example with OS-VVM CoveragePkg
A Guest Blog from Alex Grove of FirstEDA

Here in Europe, I recently had the opportunity to work with Jim Lewis, OS-VVM Chief Architect and IEEE 1076 Working Group Chair, on the first Advanced VHDL Testbenches & Verification training course....

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Why Randomize?
Guest Blog with Jim Lewis, VHDL Training Expert at SynthWorks

After presenting a conference paper on how to do OSVVM-style constrained random and intelligent coverage (randomization based on functional coverage holes), I received  a great question, "Why Randomize?"...

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90’s Kid Active-HDL Celebrates Sweet 16
Serving FPGA Designers as the tool of choice since, like, forever

As the proud Product Manager of Aldec’s  FPGA Design Simulation solution,  I am excited (like it was my first Cranberries concert) to announce that Active-HDL™ is celebrating 16 years since its initial release in 1997....

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