Aldec Design and Verification Blog Trending Articles SynthHESer - Aldec’s New Synthesis Tool Linting RISC-V designs with ALINT-PRO Enabling TySOM Zynq-based Embedded Development Board for AWS IoT Greengrass Connecting Emulated Design to External PCI Express Device Is your Verification plan pulling you in multiple directions? Try FSM Coverage How to Develop a 4K Ultra High Definition Image/Video Processing Application Using Zynq® MPSoC FPGA ARM-based SoC Co-Emulation using Zynq Boards All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications Problems Accessing Registers? – See how UVM RAL can help. As a digital design or verification engineer you know that certain features or configurations of the device can be achieved by programming some registers to set values. For example, a 32-bit register can have several fields within it... Tags:ASIC,Debugging,FPGA,Simulation,SystemVerilog,UVM,Verification Like(1) Comments (0) Read more Verification Effectiveness with Riviera-PRO: SystemVerilog Randomized Layered Testbench Understanding SystemVerilog Layered Testbench In this blog, I will discuss randomized layered testbenches used in SystemVerilog. We need to understand why we need it, ... Tags:Riviera-PRO,ASIC,Assertions,Co-simulation,Coverage,Debugging,Design,Documentation,FPGA,HDL,IEEE,OS-VVM,Randomization,Simulation,standards,SystemVerilog,UVM,Verification,Verilog Like(3) Comments (0) Read more Understanding the inner workings of UVM - Part 3 UVM Basics Part 3 of 3 In this blog, I am going to discuss different phases that UVM follows. The reason why UVM came up with such phases is because synchronization among all design-testbench was necessary. Using Verilog and VHDL,... Tags:ASIC,Co-simulation,Coverage,Debugging,Documentation,FPGA,OS-VVM,UVM,Verification Like(1) Comments (3) Read more Understanding the inner workings of UVM - Part 2 UVM Basics Part 2 of 3 In this blog, my major focus is on explaining the concepts such as Sequence, Sequencer, Driver and showing how the communication takes place from sequence to sequencer and from sequencer to driver. In the previous blog, I included... Tags:ASIC,Co-simulation,Coverage,Debugging,Documentation,FPGA,OS-VVM,UVM,Verification Like(2) Comments (0) Read more Understanding the inner workings of UVM UVM Basics Part 1 of 3 We have all been witnesses to the rapid improvements of the iPhone processor chip every year. With the iPhone 8 featuring the newest A11 Bionic at 10 nm FinFET with 4.3 billion transistors, I can’t personally fathom the amount... Tags:ASIC,Co-simulation,Coverage,Debugging,Documentation,FPGA,OS-VVM,UVM,Verification Like(2) Comments (0) Read more Beer, Cars, and Verification My thoughts after DVCon Europe As I write this, I am visiting the Aldec corporate office in the US on the day following their historical presidential election. It’s been a busy travel season for this product manager, and only a few weeks ago I was at DVCon Europe in Munich - the city of pork knuckles, beer... and of course, cars. ... Tags:Auto,Embedded,OS-VVM,SoC,UVM,VHDL Like(4) Comments (0) Read more The UVM Configuration Database Keeping a neat repository for flexible testbench structure When I want to wear a certain clothing item, I take out it of the closet. When I go shopping, I add those clothes it to my closet and there are now new items for me to pick out in the future.... Tags:Simulation,UVM,Verification Like(1) Comments (0) Read more Acceleration-Ready UVM Guest Blog by Doulos CTO, John Aynsley We hear that emulation is one of the fastest-growing segments in EDA right now, yet simulation still continues to be the main workhorse for functional verification, and SystemVerilog and UVM are everywhere you look.... Tags:Aceleration,Emulation,Hardware,SystemVerilog,UVM,Verification Like(1) Comments (0) Read more UVM Register Layer: The Structure Creating an anatomically correct model for poking and prodding. I don’t know about you, but I am looking forward to the day where we won’t even have to go to the doctor’s office for an exam. Instead, we will all have scanners in our homes that will transmit full digital models to our doctors... Tags:Simulation,UVM,Verification,Verilog Like(1) Comments (0) Read more UVM. It’s Organized and Systematic. Mastering the fundamentals One of the reasons I like using UVM is its tendency toward an organized structure and uniformity. Some may find it annoying to adhere to such a strict format in UVM, but I think it’s a good way to keep the basics of UVM engrained in your brain.... Tags:Debugging,resources,UVM,Verification Like(1) Comments (0) Read more
