SynthHESer - Aldec’s New Synthesis Tool

Sunil Sahoo, Corporate Applications Engineer
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In the early days of digital design, all circuits were designed manually. You would draw K-map, optimize the logic and draw the schematics. If you remember, we all did many logic optimization exercises back in college. It was time consuming and very error prone. This works fine for designs with  a few hundred gates, but as the designs get larger and larger this became non-feasible.

 

Designs that are described at a higher level of abstraction are less prone to human errors. High-level descriptions of designs are done without significant concern regarding design constraints. The conversion from high-level descriptions to gates is done by using synthesis tools. These tools use various algorithms to optimize the design as a whole. This circumvents the problem with different designer styles for the different blocks in the design and sub-optimal design practices. Logic synthesis tools also allows for technology independent designs. Logic synthesis technology was commercialized around 2004, and since then it’s been part of the standard EDA tool chain for ASICs and FPGAs.

 

So what is logic synthesis? Logic synthesis converts a high-level description of design into an optimized gate-level netlist. Logic synthesis uses a standard cell libraries which have simple cells, like basic logic gates(and, or, and nor), or some macro cells (adder, muxes, memory, and flip-flops). Standard cells put together are called technology library.

 

A lot of times synthesis tools especially for FPGAs can become technology specific and this can cause issues in the long run with reuse. Here at Aldec in our hardware toolchain we do use other synthesis tools for logic synthesis. But having our own logic synthesis tools in our tool chain does provide more control and integration with a complete verification flow.

 

And this is what we plan on accomplishing with our SynthHESer product. It is Aldec’s proprietary synthesis tool in our HES-DVM tool. We bench marked some designs against Vivado and we performed around 10x faster. It supports General Technology (GTech) netlist for synthesis to technology independent netlist.

 

The general benefits that this brings to our HES-DVM tool is that it provides faster synthesis and design setup in HES-DVM. It enables using FPGA vendors other than Xilinx, and makes HES-DVM not dependent on 3rd party logic synthesis tools. It also provides faster netlist processing and less memory usage, improved debug probing and HVD algorithms.

 

SynthHESer is available on both Windows and Linux. It supports all Xilinx Series 7, Ultrascale+ devices and GTech. It also has full integration with Aldec Active-HDL simulator or available in standalone command line version. It supports various kinds of attributes to better control synthesis and implementation process. It has support for mixed language synthesis for all Verilog and VHDL standards (including VHDL 2018 and SystemVerilog) and full TCL support.

 

This new tool can be accessed from Active-HDL Design Flow Manager, If you would like to try it out, go ahead and request a free evaluation license.

Sunil Sahoo provides support for customers exploring simulation tools as an Aldec Applications Engineer. His practical engineering experience includes areas in, Digital Designing, Functional Verification and Wireless Communications. He has worked in wide range of engineering positions that include Digital Design Engineer Verification Engineer and  Applications Engineer. He received his B.S. in Electronics and Communications Engineering from VIT University, India in 2008 and M.S in Computer Engineering from Villanova University, PA in 2010.

  • Products:
  • Active-HDL
  • FPGA Design Simulation,
  • HES-DVM
  • HW-Assisted Verification

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